中断处理程序不起作用

嗨，
我目前正在设计一个控制触摸屏和glcd的项目。
现在我写了两个实质性的代码，其中包括picoblazes和vhdl模块，用于与它们连接等。现在我检查了两个模块，我确信它们按照我做的各种测试的规格工作。
现在我应该说这两个代码，或者更确切地说是模块，然后通过一个信号相互连接。
这是因为一个人会打断另一个人。
所以我写了一个代码，这样我就可以处理中断，这样当信号上检测到上升沿时，另一个信号保持高电平，直到我从picoblaze上的isr读取它。
在isr的末尾，我将信号清零。这就像锁存中断源一样。
现在，当我测试这个中断处理程序时，它会再次工作，但是当我连接应该生成中断的实际硬件时，它不起作用。
例如，picoblaze正确地被中断，但当我读取isr中的锁存信号进行中断轮询时，picoblaze读取为0.因此它非常矛盾。
我甚至尝试在轮询中断源之前给出了大量的延迟，但它完全没有区别。
所以我最终得到一个被上升沿中断的电路，一个在上升沿锁存该值的电路，但我读到一个'0'。
当我通过在我正在使用的电路板的LED上输出它来检查闩锁时，它显示逻辑“1”。
即使我在isr的末尾重置了锁存器，所以它完全像垃圾一样工作，即使在各个电路的所有测试程序中，通过实现和模拟，所有电路都可以单独工作。
有没有人知道发生了什么？
有任何想法吗？



以下为原文

Hi,
I am currently designing a project which will control a touch screen and a glcd. Now i write two substantial ammount of code, which both include picoblazes and vhdl modules for interfacing with them etc. Now i checked both modules and i am sure that they work to the specifications with various tests i made. Now i should say that these two codes, or rather modules, will then interface with each other, through one signal. This is since one will interrupt the other.

  So i write a code such that i handle the interrupts in such a way that when a rising edge is detected on the signal, another signal is kept high until i read it from the isr on the picoblaze. at the end of the isr i clear the signal to 0. This is like latching the interrupt source. Now when i test this interrupt handler it works again as it should, but when i connect the actual hardware which should generate the interrupt it doesn't work.

for example, the picoblaze is interrupted correctly as it should, but when i read the latched signal in the isr for interrupt polling, the picoblaze reads a 0. So its very contradictory. I even tried giving a huge amount of delay before polling the interrupt sources but it made absolutely no difference. So i end up with a circuit which is being interrupted by a rising edge, a circuit which latches the value on a rising edge and yet i read a '0'. none the less when i check the latch by outputting it on an led of the board i am using, it shows a logic '1'. even if i do reset the latch at the end of the isr.. so it is completly working like rubbish even if under all testing procedures of the individual circuits both through implementation and simulation all circuits work well individually..

does anybody have a clue of what's going on? any ideas?