引导时的两用配置引脚保持在hi-z吗？

如果没有处于复位状态，CMOS传感器会在上电后立即驱动输出。
如果您认为这是一个问题，您可以将上拉或下拉R添加到CMOS传感器的复位输入，置位复位直到配置FPGA并且可以驱动传感器的复位引脚。
在您的帖子之后，在第2阶段和第3阶段之间，所有配置引脚都无法被主动驱动（我希望未在所选配置模式下使用的引脚保留在hi-z中）
我相信你错了。
你用我的话来表达与我的意图相反的意思。
从UG380 v2.3，第76页，“清除配置存储器（步骤2，初始化）”的说明
在此期间，除专用配置和JTAG引脚外，I / O处于高阻态。
换句话说，可以用于用户I / O的任何和所有引脚都处于高Z状态。
这意味着FPGA不会主动驱动这些引脚为高电平还是低电平。
表5-2指定了这些引脚的精确行为。
你能理解这个吗？
从ug380数据表我们知道，在第2阶段，除了配置引脚外，一切都是hi-z，在第3阶段，fpga采样M1和M2以了解使用何种配置模式并开始驱动。
这是不正确的。
你应该写的是：
从ug380数据表我们知道，在第2阶段，除了专用配置引脚外，一切都是hi-z，在第3阶段，fpga采样M1和M2以了解使用何种配置模式并开始驱动。
你同意吗？
所以我需要在启动时将cmos置于重置状态（这对我来说是其他约束的问题）
如果它不是由FPGA驱动的话，这可能是CMOS传感器复位引脚上的简单R-C网络。
或者将这些I / O与三态缓冲区接口，是吗？
如果配置引脚（不会在所选配置模式下使用）由CMOS传感器短暂驱动，即使配置引脚也（短暂地）驱动，也不会对FPGA或FPGA I / O缓冲器造成损坏。
FPGA。
请记住，这不太可能发生。
如果您需要“防弹”解决方案，请在CMOS传感器输出和FPGA引脚之间串联一个300欧姆的电阻。
即使两个器件都驱动相同的信号走线，串联电阻也会保持足够低的电流，以防止任何可能的器件损坏或闭锁。
如果您仍然不确定，请发布CMOS传感器数据表的链接（请使用英语），并指定哪些传感器引脚连接到哪些Spartan-6配置引脚。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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在原帖中查看解决方案



以下为原文

The CMOS sensor if not put in reset state drives outputs immediately after power on.
 
If you believe this is a problem, you might add a pullup or pulldown R to the reset input of the CMOS sensor, asserting the reset until the FPGA is configured and can drive the reset pin of the sensor.
 
Following your post, between phase 2 and 3 all config pins cannot be actively driven (I hoped pins not used in selected config mode remain in hi-z)
 
I believe you are mistaken.  You have taken my words to mean the opposite of what I intended.  From UG380 v2.3, page 76, description of "Clear Configuration Memory (Step 2, Initialization)"
During this time, I/Os are placed in a High-Z state except for the dedicated configuration and JTAG pins.
 
In other words, any and all pins which can be used for user I/O are placed in high-Z state.  This means the FPGA does not actively drive these pins either high or low.  Table 5-2 specifies the precise behaviour of these pins.  Does this make sense to you?
 
From ug380 datasheet we know that on phase 2 everything is hi-z except configuration pins, on phase 3 the fpga samples M1 and M2 to know what kind of configuration mode use and starts driving outs.
 
This is incorrect.  What you should have written is:
From ug380 datasheet we know that on phase 2 everything is hi-z except dedicated configuration pins, on phase 3 the fpga samples M1 and M2 to know what kind of configuration mode use and starts driving outs.
 
Do you agree?
 
 
 
so I need to put cmos in reset state (which is a problem for me for other contraints) at boot
 
This could be a simple R-C network on the CMOS sensor reset pin, if it isn't driven by the FPGA.
 
or to interface these I/Os with a threestate buffer, true?
 
If config pins (which won't be used in your selected config mode) are briefly driven by the CMOS sensor, no damage to the FPGA or FPGA I/O buffers will result, even if the config pins are also (briefly) driven by the FPGA.  Keep in mind that this is unlikely to happen.
 
If you want a 'bulletproof' solution, insert a 300-ohm resistor in series between the CMOS sensor output and the FPGA pins.  Even if both devices drive the same signal trace, the series resistor will keep currents low enough to prevent any possibliity of device damage or latchup.
 
If you are still uncertain, please post a link to the CMOS sensor datasheet (English language, please), and specify which sensor pins are connected to which Spartan-6 configuration pins.
 
-- Bob Elkind
SIGNATURE:
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在“Spartan-6配置用户指南”的UG380中，有表格描述了配置期间和之后各种配置引脚的行为。
这些相同的表格指定哪些FPGA引脚是专用配置引脚，哪些是双用途引脚。
您不能将专用配置引脚用于通用I / O.
这些表针对每种配置模式而不同，因为在各种模式中使用不同的引脚。
表5-2中列出的所有用户I / O引脚（未在所选配置模式下使用）在配置序列的第2步处于高阻态。
如果HSWAP_EN引脚拉低，表5-2还指出哪些引脚将包含内部“上拉”。
这回答了你的问题吗？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
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以下为原文

In UG380, the Spartan-6 Configuration User Guide, there are tables describing the behaviour of the various configuration pins during and after configuration.  These same tables specify which FPGA pins are dedicated configuration pins and which are dual-purpose pins.  You cannot use the dedicated configuration pins for general purpose I/O.  These tables vary for each of the configuration modes, as different pins are used in the various modes.
 
Any user I/O pins listed in Table 5-2 -- which are not used in the selected config mode --  are placed in a high-Z state at step 2 of the configuration sequence.  Table 5-2 also indicates which of these pins will include an internal 'pullup' if HSWAP_EN pin is pulled LOW.
 
Does this answer your questions?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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感谢你的回答！
在我选择的配置模式中没有使用的是我在搜索的内容，
引导序列中的模糊不清是模式位被采样
在第2阶段之后所以这并没有让我确定配置引脚的行为
在第2阶段和第3阶段之间。
软件问题可以解决而不会燃烧气味，但硬件问题没有...所以确定性更好！
非常感谢！



以下为原文

Thanks for the answer!
which are not used in the selected config mode is what I was searching,
the ambiguous thing in boot sequence was that mode bits are sampled
after phase 2 so this didn't give me the certainty of config pin's behaviour
between phase 2 and phase 3.
Software troubles can be solved without burning smell but hardware ones no...so certainty is better!
Thanks a lot!

如果您考虑一下，配置引脚必须置于hi-Z状态，直到确定主配置模式和从配置模式。
这些引脚上的有源驱动器会使接口与微型接口发生冲突/损坏，从而尝试将配置数据提供给FPGA（在从属配置模式下）。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
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以下为原文

If you think about it, the config pins must be placed in hi-Z state until determination of master vs. slave configuration mode. 
 
Active drive on these pins would conflict/corrupt the interface from a micro trying to feed config data to the FPGA (in a slave config mode).
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

是的，这肯定，事实上我计划
使用fpga从外部spi flash进行编程
在主模式下，用微处理器保持program_b低电平
如果我需要在闪存上写新的比特流（使用三态输出来避免
驱动冲突）。
我保留这些引脚仅用于编程。
我指的是表5-2中列出的其他引脚，但没有
在这个程序模式中使用...按照你说的我可能需要
三态缓冲器，因为对于电压限制，我必须主要使用bank 2
对于CMOS传感器，可能会在第2阶段和第3阶段之间开启
所有配置引脚都无法驱动，是吗？



以下为原文

Yes, this for sure, in fact I planned to
do programmation from an external spi flash with fpga
in master mode and to keep program_b low with a microprocessor
if I need to write new bitstream on flash(using threestated outputs to avoid
drive conflicts). I keep these pins only for programmation.
I was referring to the other pins that are listed in table 5-2 but not
used in this program mode... Following what you say I probably need
threestate buffers because for voltage restrictions I must use mostly bank 2
for a CMOS sensor that probably drives outs just turned on so between phase 2 and 3
all config pins cannot be driven, true?

按照你的说法，我可能需要三态缓冲器，因为对于电压限制，我必须主要使用bank 2作为CMOS传感器，可能驱动器刚刚打开，因此在阶段2和3之间所有配置引脚都无法驱动，是吗？
我不懂你的问题。
也许你可以重新说出来吗？
问候，
鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
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不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
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我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Following what you say I probably need threestate buffers because for voltage restrictions I must use mostly bank 2 for a CMOS sensor that probably drives outs just turned on so between phase 2 and 3 all config pins cannot be driven, true?

I do not understand your question.  Perhaps you can re-phrase it?
 
Regards,
 
Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

抱歉!
在我的应用程序中，我需要在2号银行上安装一个CMOS传感器
主要是多用途（配置和I / O）引脚。
对于电压和
放置限制我不能使用其他银行。
CMOS传感器
如果没有置于复位状态，则在上电后立即驱动输出。
在您的帖子之后，在第2阶段和第3阶段之间，所有配置引脚都不能
主动驱动（我希望未在所选配置模式下使用的引脚保留在hi-z中）
我需要在启动时将cmos置于重置状态（对我来说是其他约束的问题）
或者将这些I / O与三态缓冲区接口，是吗？
谢谢你的耐心！



以下为原文

Sorry!
In my application I need to put a CMOS sensor on bank 2 which has
mostly multi-purpose (configuration and I/Os) pins. For voltage and
placement constraints I cannot use other banks. The CMOS sensor
if not put in reset state drives outputs immediately after power on.
Following your post, between phase 2 and 3 all config pins cannot be
actively driven (I hoped pins not used in selected config mode remain in hi-z) so
I need to put cmos in reset state(wich is a problem for me for other contraints) at boot
or to interface these I/Os with a threestate buffer, true?
thanks for the patience!

早上好，
我很抱歉重复，但我希望尽可能清楚地预防
硬件问题或让BOM无所事事。
你让我重新说出这个问题，但是你没有回答，所以也许我不是那么清楚
在第二个表述或者其他的东西，我是这种沟通媒介（论坛）的新手
所以坦白说吧！
在我的应用程序中，我将仅使用spi主模式进行fpga配置，因此，这些是主动使用的引脚：
在多位spi的情况下，M [1：0]（m1 @ gnd，m0 @vcc），mosi，din，cso_b，cclk，init_b，done和program_b加上其他两位。
从ug380数据表我们知道，在第2阶段，除了配置引脚外，一切都是hi-z，在第3阶段，fpga采样M1和M2以了解使用何种配置模式并开始驱动。
另一方面，我们在表5-2中列出了其他配置位（例如A0到A25，scp0到scp7），这些配置位在这种配置模式（spi）中没有使用，但它们实际上是配置位。
以下数据表在第二阶段和第二阶段之间，我们不确定他们的行为。
所以，我的问题是，如果我在这些引脚中放置三态缓冲区，即使它们没有在配置中使用，它会更好吗？
有什么东西逃脱了我？



以下为原文

goodmorning,
I'm sorry bob to be repetitive but I want to have things as clearer as possible to prevent
hardware troubles or getting BOM growing for nothing.
You asked me to re-phrase the question but you didn't answer, so maybe I wasn't  so clear
in second formulation too  or maybe something else, i'm new to this kind of communication medium (forums)
so feel free to be frank!
In my application I will use ONLY spi master mode for fpga configuration so, these are pins actively used:
M[1:0](m1@gnd, m0@vcc), mosi, din,cso_b,cclk, init_b,done and program_b plus other two bits in case of multi bit spi.
From ug380 datasheet we know that on phase 2 everything is hi-z except configuration pins, on phase 3 the fpga samples M1 and M2 to know what kind of configuration mode use and starts driving outs.
On the other hand we have other configuration bits (for example A0 to A25, scp0 to scp7) listed in table 5-2 that are not used in this configuration mode(spi) but that are effectively configuration bits. following datasheet Between phase two and three we aren't assured of their behaviour.  So, my question is, is it better if i put threestate buffers in these pins even if they aren't used in configuration? There is something that escapes me?

如果没有处于复位状态，CMOS传感器会在上电后立即驱动输出。
如果您认为这是一个问题，您可以将上拉或下拉R添加到CMOS传感器的复位输入，置位复位直到配置FPGA并且可以驱动传感器的复位引脚。
在您的帖子之后，在第2阶段和第3阶段之间，所有配置引脚都无法被主动驱动（我希望未在所选配置模式下使用的引脚保留在hi-z中）
我相信你错了。
你用我的话来表达与我的意图相反的意思。
从UG380 v2.3，第76页，“清除配置存储器（步骤2，初始化）”的说明
在此期间，除专用配置和JTAG引脚外，I / O处于高阻态。
换句话说，可以用于用户I / O的任何和所有引脚都处于高Z状态。
这意味着FPGA不会主动驱动这些引脚为高电平还是低电平。
表5-2指定了这些引脚的精确行为。
你能理解这个吗？
从ug380数据表我们知道，在第2阶段，除了配置引脚外，一切都是hi-z，在第3阶段，fpga采样M1和M2以了解使用何种配置模式并开始驱动。
这是不正确的。
你应该写的是：
从ug380数据表我们知道，在第2阶段，除了专用配置引脚外，一切都是hi-z，在第3阶段，fpga采样M1和M2以了解使用何种配置模式并开始驱动。
你同意吗？
所以我需要在启动时将cmos置于重置状态（这对我来说是其他约束的问题）
如果它不是由FPGA驱动的话，这可能是CMOS传感器复位引脚上的简单R-C网络。
或者将这些I / O与三态缓冲区接口，是吗？
如果配置引脚（不会在所选配置模式下使用）由CMOS传感器短暂驱动，即使配置引脚也（短暂地）驱动，也不会对FPGA或FPGA I / O缓冲器造成损坏。
FPGA。
请记住，这不太可能发生。
如果您需要“防弹”解决方案，请在CMOS传感器输出和FPGA引脚之间串联一个300欧姆的电阻。
即使两个器件都驱动相同的信号走线，串联电阻也会保持足够低的电流，以防止任何可能的器件损坏或闭锁。
如果您仍然不确定，请发布CMOS传感器数据表的链接（请使用英语），并指定哪些传感器引脚连接到哪些Spartan-6配置引脚。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
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以下为原文

The CMOS sensor if not put in reset state drives outputs immediately after power on.
 
If you believe this is a problem, you might add a pullup or pulldown R to the reset input of the CMOS sensor, asserting the reset until the FPGA is configured and can drive the reset pin of the sensor.
 
Following your post, between phase 2 and 3 all config pins cannot be actively driven (I hoped pins not used in selected config mode remain in hi-z)
 
I believe you are mistaken.  You have taken my words to mean the opposite of what I intended.  From UG380 v2.3, page 76, description of "Clear Configuration Memory (Step 2, Initialization)"
During this time, I/Os are placed in a High-Z state except for the dedicated configuration and JTAG pins.
 
In other words, any and all pins which can be used for user I/O are placed in high-Z state.  This means the FPGA does not actively drive these pins either high or low.  Table 5-2 specifies the precise behaviour of these pins.  Does this make sense to you?
 
From ug380 datasheet we know that on phase 2 everything is hi-z except configuration pins, on phase 3 the fpga samples M1 and M2 to know what kind of configuration mode use and starts driving outs.
 
This is incorrect.  What you should have written is:
From ug380 datasheet we know that on phase 2 everything is hi-z except dedicated configuration pins, on phase 3 the fpga samples M1 and M2 to know what kind of configuration mode use and starts driving outs.
 
Do you agree?
 
 
 
so I need to put cmos in reset state (which is a problem for me for other contraints) at boot
 
This could be a simple R-C network on the CMOS sensor reset pin, if it isn't driven by the FPGA.
 
or to interface these I/Os with a threestate buffer, true?
 
If config pins (which won't be used in your selected config mode) are briefly driven by the CMOS sensor, no damage to the FPGA or FPGA I/O buffers will result, even if the config pins are also (briefly) driven by the FPGA.  Keep in mind that this is unlikely to happen.
 
If you want a 'bulletproof' solution, insert a 300-ohm resistor in series between the CMOS sensor output and the FPGA pins.  Even if both devices drive the same signal trace, the series resistor will keep currents low enough to prevent any possibliity of device damage or latchup.
 
If you are still uncertain, please post a link to the CMOS sensor datasheet (English language, please), and specify which sensor pins are connected to which Spartan-6 configuration pins.
 
-- Bob Elkind
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好！
现在一切都很清楚！
非常感谢！



以下为原文

Ok! Now everything is clear!
Thanks a lot!