是否必须将主时钟与辅助时钟重新同步？

保罗，
亚稳定性不是世界末日。
如果信号很重要（您必须知道它是零还是一个），则需要同步器。
阶段的数量仅使亚稳态的发生频率降低（它永远不会完全消失）。
一个很好的例子是键盘：如果你键入并获得错误的字符，你可以退格，并输入正确的字符。
不需要额外的阶段。
键入的异步性质和系统采样对于偶尔的亚稳状态是好的，并且字符不想要你想要的（因为打碎的位从未稳定，并且产生了一些随机字符）。
不能容忍亚稳态的情况的一个很好的例子是FIFO中的满标志和空标志。
输入上的时钟正在填充FIFO，输出上的时钟正在清空FIFO。
如果满标志变为亚稳态，则可能会尝试将FIFO填满过满（丢失一个值），或者您可能认为FIFO已满，而不是。
对于这种情况，同步器是强制性的良好工程。
通常，满标志几乎已满（一个或多个比实际完全少），以使FIFO在您的设计中更加健壮。
因此发生亚稳态信号。
仅仅因为它可能是'避免它是糟糕的工程。
同步器可以在需要它们的地方使用，并且它的亚稳定频率很重要。
同步器不能消除亚稳态，它只会降低发生率。
Austin Lesea主要工程师Xilinx San Jose
在原帖中查看解决方案



以下为原文

Paul,

Metastability is not the end of the world.  If the signal is important (you must know if it is zero or one) then a synchronizer is required.  The number of stages only makes the occurence of the metastable condition less frequent (it never goes away completely).

A good example is of a keyboard:  if you type and get the wrong character, you back-space, and type the right one.  No extra stages are required.  The asynchrnous nature of typing, and the system sampling is just fine with the occasional metastable state, and the character being not want you wanted (because the smapled bits never stabalized, and some random character resulted).

A good example of a case where metastability is not to be tolerated is in a FIFO for the full, and empty flags.  The clock on the input is filling the FIFO, the clock on the output is emptying the FIFO.  If the full flag goes metastable, you might try to fill the FIFO to over-full (lose a value), or you might think the FIFO is full, when it isn't.  For this case, the synchronizer is mandatory good engineering.  Often, the full flag is almost full (one or more less than really full), to make the FIFO more robust in your design.
 
So a signal being metastable happens.  Avoiding it just because it 'might be' is poor engineering.  Synchronizers get used where they are needed, and how often it goes metastable is important.  The synchronizer does not eliminate metastability, it only reduces the occurence rate.
 
Austin Lesea
Principal Engineer
Xilinx San JoseView solution in original post

对于单个信号，2个FF可以很好地工作。如果你有并行数据总线，你应该使用FIFO。
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

For a single signal, 2 FFs will do nicely.

If you have a parallel data bus, you ought to use a FIFO.

------------------------------------------
"If it don't work in simulation, it won't work on the board."

保罗，
亚稳定性不是世界末日。
如果信号很重要（您必须知道它是零还是一个），则需要同步器。
阶段的数量仅使亚稳态的发生频率降低（它永远不会完全消失）。
一个很好的例子是键盘：如果你键入并获得错误的字符，你可以退格，并输入正确的字符。
不需要额外的阶段。
键入的异步性质和系统采样对于偶尔的亚稳状态是好的，并且字符不想要你想要的（因为打碎的位从未稳定，并且产生了一些随机字符）。
不能容忍亚稳态的情况的一个很好的例子是FIFO中的满标志和空标志。
输入上的时钟正在填充FIFO，输出上的时钟正在清空FIFO。
如果满标志变为亚稳态，则可能会尝试将FIFO填满过满（丢失一个值），或者您可能认为FIFO已满，而不是。
对于这种情况，同步器是强制性的良好工程。
通常，满标志几乎已满（一个或多个比实际完全少），以使FIFO在您的设计中更加健壮。
因此发生亚稳态信号。
仅仅因为它可能是'避免它是糟糕的工程。
同步器可以在需要它们的地方使用，并且它的亚稳定频率很重要。
同步器不能消除亚稳态，它只会降低发生率。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Paul,

Metastability is not the end of the world.  If the signal is important (you must know if it is zero or one) then a synchronizer is required.  The number of stages only makes the occurence of the metastable condition less frequent (it never goes away completely).

A good example is of a keyboard:  if you type and get the wrong character, you back-space, and type the right one.  No extra stages are required.  The asynchrnous nature of typing, and the system sampling is just fine with the occasional metastable state, and the character being not want you wanted (because the smapled bits never stabalized, and some random character resulted).

A good example of a case where metastability is not to be tolerated is in a FIFO for the full, and empty flags.  The clock on the input is filling the FIFO, the clock on the output is emptying the FIFO.  If the full flag goes metastable, you might try to fill the FIFO to over-full (lose a value), or you might think the FIFO is full, when it isn't.  For this case, the synchronizer is mandatory good engineering.  Often, the full flag is almost full (one or more less than really full), to make the FIFO more robust in your design.
 
So a signal being metastable happens.  Avoiding it just because it 'might be' is poor engineering.  Synchronizers get used where they are needed, and how often it goes metastable is important.  The synchronizer does not eliminate metastability, it only reduces the occurence rate.
 
Austin Lesea
Principal Engineer
Xilinx San Jose

嗨奥斯汀，
谢谢你的好解释。
我还有一个问题。
在必须检测起始位的下降沿/上升沿的异步通信中会发生什么？
有一些接口，如RS232，可以使用错误处理功能，如果出现错误，则重新发送数据。
RS232不是一个实时接口，所以几毫秒或更少，这不是什么大不了的事。
另一方面，存在一些异步接口（例如，实时，用于运动控制），其中必须高度重视传输中的一个错误并且必须关闭整个机器。
通信失败的后果可能非常严重。
人们（我的意思是专家，而不是像我这样的设计师：笑脸快乐:)处理这种情况 - 我的意思是他们如何处理/避免/最小化关键应用中的亚稳态。
您能否给我一些链接或指示，从中可以了解更多有关Xilinx FPGA中亚稳态的信息？
谢谢，
保罗



以下为原文

Hi Austin,
 
Thanks for the nice explanation.
 
I still have one question. What happens in an asynchronous communication where the falling/rising edge of a start bit must be detected?
There are interfaces like RS232 where error handling functions can be used and in case of error, data is resent. RS232 is not a real time interface so several milliseconds less or more it's not a big deal.
 
On the other side there are some asynchronous interfaces (e.g. real-time, used in motion control) where one error in the transmission must be treated with high importance and the entire machine must be shut-down. The consequences of a communication failure could be pretty severe. 
 
How people (I mean experts and not designers like me :smileyhappy: ) handle this kind of situation - I mean how do they treat/avoid/minimize metastability in critical applications.
 
Can you please give me some links or directions from where I can learn more about metastability in Xilinx FPGAs?
 
Thanks,
Paul

在必须检测起始位的下降沿/上升沿的异步通信中会发生什么？
奥斯汀描述了亚稳态避免。
检测异步串行起始位会增加类似但不同的时钟域对齐问题。
未能将信号与时钟域对齐是状态机锁定的一个非常常见的原因，并且大多数（可能是所有）异步串行接收器都实现为状态机。
建议你阅读这两个描述尽可能多的单词时钟域对齐的线程：这一个（在线程中读取＃2）和这一个（在这个帖子中读取第32个帖子）。
这是我对亚稳态的最喜欢的解释（见线程中的第15页）。
有像RS232这样的接口，可以使用错误处理功能
使用，如果出现错误，则重新发送数据。
RS232不是实时的
界面如此几毫秒或更少，这不是什么大不了的事。
在异步串行链路中，此类错误处理功能极为罕见。
通常，它们是在数据包（非字符）的基础上实现的。
通常，它们是用软件实现的，而不是硬件。
另一方面，有一些异步接口（例如
实时，用于运动控制）传输中的一个错误
必须高度重视，整个机器必须
关掉。
沟通失败的后果可能很糟糕
严重。
你正朝着正确的方向领导讨论！
但你太谦虚了。
遭受非对齐输入的状态机实现将经常锁定 - 经常。
锁定或损坏率为20％太高，即使对于“非关键”串行链路也是如此。
如果基于数据包实现“错误恢复”（例如，20个字符的数据包），则20％的字符失败或锁定速率将保证错误恢复机制几乎永远不会成功。
人们（我的意思是专家而不是像我这样的设计师）处理这种情况 - 我的意思是他们如何处理/避免/最小化关键应用中的亚稳态。
由于状态机设计在FPGA设计中如此常见，并且由于异步输入引起的状态机锁定现象非常普遍，因此通常在逻辑设计人员的职业生涯中很早就会学到时钟域对齐的教训。
如果继续进行逻辑设计，真的没有办法避免学习本课。
另一方面，真正的经典亚稳态问题（正如奥斯汀所描述的那样）并不常见。
如此不可避免的时钟域对准措施也将有效地解决亚稳避免问题。
您能否给我一些链接或指示，从中可以了解更多有关Xilinx FPGA中亚稳态的信息？
Xilinx FPGA在应用和处理这些问题方面没有什么独特之处 - 除了这么多设计师广泛使用它们的现实。
所描述的两个问题并不复杂，这些主题的许多帖子（包括Austin，Gabor，Eilert，Bassman，我和其他人的帖子）应该坚定地推动课程（问题，概念和解决方案）
进入你的大脑。
另一方面......这是一个线索，可怜的设计师在＃11的帖子中获得了“答案”，并且直到帖子＃25（到目前为止）运行到52个帖子之后才接受建议！
解决方案（他的一个问题）太简单了。
哦，好吧......与此同时，我们继续阅读，发布和学习......希望我们能够在此过程中完成一些创收工作。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

What happens in an asynchronous communication where the falling/rising edge of a start bit must be detected?

Austin described metastable state avoidance.  Detection of an async serial start bit adds a similar -- but different -- problem of clock domain alignment.  Failure to align signals to a clock domain is a very common cause for state machine lockup, and most (perhaps all) async serial receivers are implemented as state machines.  Suggest you read these two threads which describe clock domain alignment in as many words as possible:  this one (read post #2 in the thread) and this one  (read the 32nd! post in this thread).  And this is my favourite explanation of metastability (see post #15 in the thread).

There are interfaces like RS232 where error handling functions can be used and in case of error, data is resent. RS232 is not a real time interface so several milliseconds less or more it's not a big deal.

Such error handling capabilities are extremely rare in async serial links.

• Typically they are implemented on a packet (not character) basis.
  
• Typically they are implemented in software, not hardware.
  

On the other side there are some asynchronous interfaces (e.g. real-time, used in motion control) where one error in the transmission must be treated with high importance and the entire machine must be shut-down. The consequences of a communication failure could be pretty severe.

You are leading the discussion in the right direction!  But you are too modest.  A state machine implementation which suffers from non-aligned inputs will lock up often -- very often.  A lock-up or corruption rate of 20% is too high, even for 'non-critical' serial links.  If 'error recovery' is implemented on a packet basis (for example, a 20-character packet), a 20% character failure or lockup rate would guarantee that the error recovery mechanism would almost never succeed.

How people (I mean experts and not designers like me) handle this kind of situation - I mean how do they treat/avoid/minimize metastability in critical applications.

Because state machine designs are so common in FPGA design, and because the phenomenon of state machine lockup due to async inputs is so common, the lesson of clock domain alignment is usually learned very early in a logic designer's career.  There's really no way to avoid learning this lesson if you continue in logic design.
 
On the other hand, true classic metastable problems (as Austin very nicely describes) are much less common.  The clock domain alignments measures which are so unavoidable will also effectively address the metastable avoidance problem.

Can you please give me some links or directions from where I can learn more about metastability in Xilinx FPGAs?

There is nothing unique about Xilinx FPGAs in the application and handling of these problems -- other than the reality that they are used so broadly by so many designers.
 
The two problems described aren't that complicated, and the many posts on these subjects (including the posts by Austin, Gabor, Eilert, Bassman, myself, and others) should drive the lessons (the problems, concepts, and the solutions) firmly into your brain.
 
On the other hand...  here's a thread where the poor designer was given "the answer" in post #11, and didn't accept the advice until post #25 of a thread which (so far) runs to 52 posts!  The solution (to one of his problems) was too simple to accept.  Oh well...  in the meantime we keep reading, posting, and learning...  and hopefully we get some income-generating work done along the way.
 
-- Bob Elkind
SIGNATURE:
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Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
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