SPI从时钟使用实际的SCK有什么问题

你好。
我正在为一个自定义界面工作
设备（在vhdl中）基本上与SPI从设备操作相同
在模式3中，在实现中存在一些问题。
当我模拟
它，它按照预期执行但在我的spartan3e上测试时不那么好
开发板。
在我试图追查
问题，我看了SPI Slave核心的其他在线示例和我
注意到他们所有人都通过重复采样来看SCK线
（在较高的频率，然后SCK）由外部时钟确定。
SCK的上升沿和下降沿通过取多个来确定
样本。
相反，使用实际的SCK有什么问题
输入作为时钟源并具有由其上升和触发的事件
下降边缘？
我看到的差异是SCK信号是
仅在传输过程中运行，也可能需要运行
连接到时钟输入。



以下为原文

hi there.
I'm currently working on a custom interface for adevice (in vhdl) that is basically identical to an SPI slave operatingin mode 3 andam having some problems in implementation. When I simulateit, it performs as desired but not so great when tested on my spartan3edevelopment board.

in my attempt to track down theproblem, i looked at other online examples of SPI Slave cores and Inoticed that all of them look at the SCK line by sampling it repeatedly(at a higher frequency then SCK) determined by an external clock.Rising and falling edges of SCK are determined by taking multiplesamples. Instead, is there anything wrong with using the actual SCKinput as the clock source and have events triggered by its rising andfalling edges?
The difference I see is that the SCK signal isonly operating during transmission and would also likely need to beconnected to a clock input.