CPLD XC9500是否有任何序列？

gopal_amlekar写道：由于我没有在CPLD子论坛中得到任何回复，因此在此论坛中发布此帖子。
你好，
我想了解一些关于CPLD编程的事情。
FPGA遵循配置顺序。
对于例如
XAPP188第11页的表7显示了传输比特流的设备配置顺序。
同样，CPLD XC9500是否有任何序列？
我所理解的是.jed文件是在SHIFT-DR状态下而不是.bit文件传输的。
它是否正确？
传输.jed文件后，XC9500是否还需要JSTART指令并切换到Run-Test-Idle状态？
是否传输了整个.jed文件，或者是否有一些标题或类似信息被跳过？
感谢你的支持... 
你很困惑。
您可以编程FPGA配置EPROM。
在上电或以其他方式命令时，FPGA读取此EPROM并进行自我配置，这基本上意味着它会在FPGA中加载SRAM单元，以控制资源如何用于您的设计。
但是，CPLD没有SRAM单元，您可以直接对其配置进行编程。
所以你对编程或配置感到困惑吗？
----------------------------是的，我这样做是为了谋生。



以下为原文

gopal_amlekar wrote:
Posting this thread in this forum since I did not get any response in CPLD subforum.
 
Hello,
 
I want to understand a few things about CPLD programming.
 
There is a configuration sequence followed for FPGA. For e.g. XAPP188 Table 7 on page 11 shows the device configuration sequence to transfer a bit stream.
 
Similarly, is there any sequence for CPLD XC9500?
 
What I understood is that the .jed file is transferred instead of .bit file in the SHIFT-DR state. Is this correct?
After transferring the .jed file does XC9500 also need the JSTART instruction and switching to Run-Test-Idle state?
 
Is the entire .jed file transferred or there is some header or similar information which is skipped?
 
Thanks for support...

You're very confused.
 
You program the FPGA configuration EPROM. At power-up or when otherwise commanded, the FPGA reads this EPROM and configures itself, which basically means that it loads the SRAM cells in the FPGA that control how the resources are used for your design.
 
However, a CPLD has no SRAM cells and you program its configuration directly. 
 
So are you confused about programming or configuration?
----------------------------Yes, I do this for a living.

你好bassman59
非常感谢你的回复。
我对CPLD编程特别是XC9500感到困惑（目前使用的是XC95108）。
我能够解码jedec文件。
但是，如何将信息传输到CPLD？
我认为还有一些扇区地址也与jedec文件保险丝数据一起发送。
如何计算这些地址？
此外，在擦除CPLD时，在发送擦除命令后发送扇区地址？
如何找到这些地址？
感谢致敬，



以下为原文

Hello bassman59
 
Many thanks for a reply.
 
I am confused about CPLD programming specifically XC9500 (Presently using XC95108). I am able to decode a jedec file. But how exactly the information is transferred to CPLD? I think there are some sector addresses also sent along with the jedec file fuse data. How to calculate these addresses?
 
Also, while erasing a CPLD, the sector addreses are sent out after sending erase command? How to find out these addresses?
 
Thanks and regards,

gopal_amlekar写道：你好bassman59
非常感谢你的回复。
我对CPLD编程特别是XC9500感到困惑（目前使用的是XC95108）。
我能够解码jedec文件。
但是，如何将信息传输到CPLD？
我认为还有一些扇区地址也与jedec文件保险丝数据一起发送。
如何计算这些地址？
你仍然感到困惑，没有回答我的问题。
您想知道如何编程CPLD吗？
或者您想知道CPLD如何从其EEPROM单元中进行配置？
前者：它看起来基本上像一个EEPROM，器件具有内部逻辑，通过JTAG获取数据并做正确的事情。
后者：为什么这很重要？
基本上，它不像FPGA一样“配置”。
当它开机时它“是”。
此外，在擦除CPLD时，在发送擦除命令后发送扇区地址？
如何找到这些地址？
感谢致敬， 
打开一个webcase并直接询问Xilinx。
你为什么在乎？
您是否尝试实施自己的iMPACT程序版本？
祝你好运。
----------------------------是的，我这样做是为了谋生。



以下为原文

gopal_amlekar wrote:
Hello bassman59
 
Many thanks for a reply.
 
I am confused about CPLD programming specifically XC9500 (Presently using XC95108). I am able to decode a jedec file. But how exactly the information is transferred to CPLD? I think there are some sector addresses also sent along with the jedec file fuse data. How to calculate these addresses?

You're still confused and have not answered my question. Do you want to know how you how you program the CPLD? Or do you want to know how the CPLD configures itself from its EEPROM cells?
 
The former: it looks essentially like an EEPROM and the device has internal logic which takes data over JTAG and does the right thing.
 
The latter: why does this matter? Basically, it doesn't "configure" like an FPGA. It "is" when it's powered on.

 Also, while erasing a CPLD, the sector addreses are sent out after sending erase command? How to find out these addresses?
 
Thanks and regards,

Open a webcase and ask Xilinx directly. Why do you care? Are you trying to implement your own version of the iMPACT program? Good luck with that.
----------------------------Yes, I do this for a living.

bassman59写道：你仍然困惑，没有回答我的问题。
您想知道如何编程CPLD吗？
或者您想知道CPLD如何从其EEPROM单元中进行配置？
我想了解前者，如何从Impact编程CPLD。
我不关心编程后CPLD内部会发生什么。
因此，在编程时，它首先被删除。
发送到CPLD进行擦除的命令和参数是什么？
同样，如何使用Jedec文件数据对CPLD进行编程？
任何帮助将不胜感激。
谢谢...



以下为原文

bassman59 wrote:
You're still confused and have not answered my question. Do you want to know how you how you program the CPLD? Or do you want to know how the CPLD configures itself from its EEPROM cells?

I want to know about the former, how a CPLD is programmed from Impact. I dont care about what happens inside the CPLD after programming.
So while programming, it is first erased. What are the commands and paramters sent to CPLD for erasing? Similarly how Jedec file data is used to program the CPLD?
 
Any help will be appreciated.
 
Thanks...