输入与输出不一样？

你好，
我正在测试一个新的基于SPARTAN 3AN的电路板。
为了测试我是否能够对FPGA进行编程，我宣布了一个具有两个信号的顶级实体。
一个输入和一个输出。
输入连接到40MHz时钟，输出连接到浮动测试点。
在架构中，我有一个声明说输入信号分配给输出信号。生成.mcs文件并用它编程FPGA，当我用示波器观察电路板上的输入和输出引脚（测试点）时，输入它
是一个很好的40MHz时钟。
在输出测试点，它大约是40MHz的时钟，但是当用输入时钟触发时，时钟在屏幕上滚动。
意思是，输出时钟比输入时钟慢约5-10 Hz。
FPGA（因为，VHDL对输入信号的性质一无所知，因此FPGA中没有PLL或时钟管理器）应该只是作为该信号的传递，即使使用IBUF或OBUF，我也看不到
FPGA如何改变信号。
关于如何发生这种情况的任何想法？
谢谢..



以下为原文

Hello,

I was testing a new SPARTAN 3AN based board. Just to test that I was able to program the FPGA, I declared a top level entity with two signals. One input and one output. Input was connected to a 40MHz clock and output is connected to a floating test point. In architecture, I have one statement saying input signal is assigned to output signal. After generating .mcs file and programing the FPGA with it, when I was observing the input and output pins (test points) on the circuit board using oscilloscope, at input it was a good 40MHz clock. At output test point, it was about 40MHz clock, but the clock was rolling across the screen when triggerred with input clock. Meaning, the output clock was about 5-10 Hz slower than input clock. The FPGA (since, VHDL did not have any idea about nature of input signal, so PLL or clock managers were not present in FPGA) should just act as pass through for that signal, even with use of IBUF or OBUF, I do not see how the signal would be changed by FPGA.

Any ideas on how this could occur?

Thanks..