如何为连接反馈的两个晶体管提供偏置电容

模拟端口（Term）在所有频率下均为50欧姆，低至DC。
您需要在电路的输入和输出处放置一个DC_Block。



     以下为原文

  The simulation ports (Term) are 50 Ohm at all frequencies, down to DC. 
You need to place a DC_Block at the input and output of your circuit.

> {quote：title = nimbargi写道：} {quote}>当我使用单个ATF54143晶体管时，我没有遇到任何问题。
在固定端口DC模块后，T1的栅极电压现在看起来很好。
现在你必须修理你的电路。
在原理图中，您已将T1漏极连接到T2源（这是您想要的吗？）和T2门是浮动的（对于DC）。
这看起来不对。



     以下为原文

  > {quote:title=nimbargi wrote:}{quote}
> When I work with single ATF54143 transistor, I didn't get any problem. 

After fixing the port DC block, the gate voltage at T1 looks good now.

Now you have to fix your circuit. In your schematic, you have connected T1 drain to T2 source (is this what you want?)  and T2 gate is floating (for DC).  This doesn't look right.

好的我明白了。
但是你需要T2门的偏置电压。
这是您参考中的BIAS2。
对于T2，您应该将S2连接到S1，而不是将其连接到地面。编辑：volker_muehlhaus于2014年1月10日上午10:33



     以下为原文

  Ok, I see.    But you will need bias voltage at T2 Gate. That is BIAS2 in your reference.

And for T2, you should connect S2 to S1, instead of connecting it to ground.

Edited by: volker_muehlhaus on Jan 10, 2014 10:33 AM

> {quote：title = volker_muehlhaus写道：} {quote}>好的，我明白了。
但是你需要T2门的偏置电压。
这是您参考中的BIAS2。
>>对于T2，您应该将S2连接到S1，而不是将其连接到地。
>>编辑：volker_muehlhaus于2014年1月10日上午10:33对于T2，您应该将S2连接到S1，而不是将其连接到地面。“Volker Sir，我们如何将S2连接到S1用于T2，两个来源都是
在内部连接时，T2的源极S1的一端连接到T1的漏极D，T2的S2的另一端或者原样保持原样（原样打开）或者连接到地



     以下为原文

  > {quote:title=volker_muehlhaus wrote:}{quote}
> Ok, I see.    But you will need bias voltage at T2 Gate. That is BIAS2 in your reference.
> 
> And for T2, you should connect S2 to S1, instead of connecting it to ground.
> 
> Edited by: volker_muehlhaus on Jan 10, 2014 10:33 AM
And for T2, you should connect S2 to S1, instead of connecting it to ground."

Volker Sir,
              How we can connect S2 to S1 for T2, both sources are internally connected , one end of source S1 of T2 is connected to drain D of T1, other end of S2 of T2 either leave as it is(open it as it is) or connected to the ground

如此处和其他地方所述，您需要做两件事：1。为晶体管X2的栅极提供必要的偏置。
2.将接地连接更改为两个设备上的S2引脚。
S1和S2源连接在内部连接，因此如果您将其中一个接地，则另一个也接地。
因此，晶体管X1的漏极和TL2的两个引脚也有效地接地。
连接到S1的任何内容实际上与连接到任一设备的S2的任何内容并行。
接地连接会使与其他源极引脚连接的任何东西短路。
如果你将S1和S2连接到X1的TL2和X2的X1的漏极至少源极电流将在源极引脚对之间共享（模拟器有时会抱怨未连接的引脚，如果你为这个设计创建布局，最终你
无论如何都需要连接两个引脚）。



     以下为原文

  As has been explained here, and elsewhere, you need to do 2 things:

1. Provide the necessary bias to the gate of transistor X2.

2. Change the grounded connections to the S2 pins on both devices. The S1 and S2 source connections are connected internally so if you ground one ofthem then the other is also grounded. Therefore, the drain of transistor X1 and both pins of TL2 are effectively grounded too. Anything you connect to S1 is effectively in parallel with whatever is connected to S2 of either device. Ground connections will short anything connected to the other source pin. If you connect both S1 and S2 to TL2 for X1 and the drain of X1 for X2 at least the source current will be shared between the source pin pairs (simulators sometimes complain about unconnected pins and also if you create the layout for this design eventually you will need to make connections to both pins anyway).

该电路完全不正确。
你有3,500安培（3.48 kA）通过X2的源，因为直流，MLIN实际上是一个短（或至少非常小的电阻），因此3V直流电源通过TL12，X2 S1到X2直接连接到地
S2和TL13。
你再次错误地发现了X2的源极引脚。
它们应该连接到X2的漏极而不是只连接到另一个接地的漏极。
2. 3V电源应仅连接到X2和非X1的漏极。
X1的漏极应仅连接到X2的两个源极引脚。
3.施加到X2栅极的偏压与用于X1栅极的偏压不同。
如果两个器件都需要相同的漏极电流，则两者的Vgs应该相似，但由于源电压不同，栅极电压也应该不同。



     以下为原文

  That circuit is totally incorrect. You have 3,500 Amps (3.48 kA) passing through the source of X2 as at DC the MLINs are effectively a short (or at least a very small resistance) and therefore the 3V DC source is connected directly to ground through TL12, X2 S1 to X2 S2 and TL13.

1. You have the source pins of X2 wrong again. They should BOTH be connected to the drain of X2 and not just one connected with the other one grounded.

2. The 3V source should only be connected to the drain of X2 and NOT X1. The drain of X1 should only be connected to both source pins of X2.

3. The bias applied to the gate of X2 is NOT the same voltage as that used for the gate of X1. Vgs for both should be similar if the same drain current is required through both devices but as the source voltages are different then the gate voltage should be different also.

sdgrant Sir，在这里，我附上两个TRANSISTOR BIASING的.ZAP文件。



     以下为原文

  sdgrant Sir,
         Here with , I am attaching the .ZAP file of TWO TRANSISTOR BIASING.

附件

• TWO_TRANSISTOR_BIASING.zap34.3 KB
  

您的原理图仍然不正确，因为您已将3V连接到X2的漏极和源极引脚以及X1的漏极引脚。
它应该只连接到X1的漏极引脚。
在连接到TL12和X1的漏极之前，从TL13下降的示意线应该简单地穿过3V导线，并且不应该连接到3V导线。



     以下为原文

  Your schematic is still incorrect as you have connected 3V to both the drain and source pins of X2 and the drain pin of X1. It should only be connected to the drain pin of X1. The schematic wire that drops down from TL13 should simply cross the 3V wire, before connecting to TL12 and the drain of X1, and should NOT be connected to the 3V wire.

不幸的是我在上一篇文章中错误地提到了晶体管参考。
3V应仅连接到X2的漏极引脚而不是X1。
TL12和TL13只能连接到X1的漏极引脚。
您真的需要将此原理图与原始参考电路进行比较，然后连接应该是显而易见的。



     以下为原文

  Unfortunately I got the transistor reference wrong in my last post. The 3V should only be connected to the drain pin of X2 and not X1. It is TL12 and TL13 that should only connect to the drain pin of X1.

You really need to compare this schematic with your original reference circuit and then the connectivity should be obvious.

> {quote：title = nimbargi写道：} {quote}>还有一个澄清，现在我在晶体管X1和X2的两个源处得到相同的电流，现在我可以在两个晶体管的栅极连接相同的电压。
*这绝对不正确。* X1门和X2门的电压必须不同，X1.V~G~不等于X2.V~G~。
类似地，X1.V~D~将不等于X2.V~D~。
两个晶体管有效地堆叠在一起，X2高于X1，因此X2引脚的绝对电压将大于X1上的绝对电压。
你可以做的是让两个器件偏置在相似的状态是X1.V~GS~与X2.V~GS~和X1.V~DS~相同，与X2.V~DS~相同，但那是
完全不同于将X1.V~G~与X2.V~G~和X1.V~D~相同，与X2.V~D~相同。
你可以说在这种情况下X1.V~G~相当于X1.V~GS~和X1.V~D~相当于X1.V~DS~，因为X1的源极引脚接地。
对于X2上的任何电压都不是这样。



     以下为原文

  > {quote:title=nimbargi wrote:}{quote}
>                 One more clarification , now I am getting the same  currents at the two sources of the transistors X1 and X2, now I can connect the same voltage at the gate of two transistors.

*That is absolutely incorrect.* The voltage at X1 gate and X2 gate MUST be different, X1.V ~G~ is not equal to X2.V ~G~. Similarly X1.V ~D~ will not be equal to X2.V ~D~. The two transistors are effectively stacked on on top of one another, X2 above X1, so the absolute voltages at the pins of X2 will be greater than those on X1.

What you could do to have both devices biased in similar states is that X1.V ~GS~ would be the same as X2.V ~GS~ and X1.V ~DS~ the same as X2.V ~DS~ but that is totally different to comparing X1.V ~G~ to be the same as X2.V ~G~ and X1.V ~D~ to be the same as X2.V ~D~.

You can say that in this case X1.V ~G~ is equivalent to X1.V ~GS~ and X1.V ~D~ is equivalent to X1.V ~DS~ as the source pin of X1 is grounded. This is not true for any voltages on X2.

> {quote：title = nimbargi写道：} {quote}>但我采用了ATF54143 3V，60mA晶体管。
正如我之前在X1排水时所说，我得到的是89.2mv和59.8mA。
同样地，我正在消耗X2电压，电流为3v，59.8mA。
>在漏极X1（89.2mV）处的电压是否正常（这个电压晶体管工作得多吗？），否则我们必须在X1的漏极处得到3v，因为我们采用了3v，60mA ATF54143晶体管
。
你显然不明白V~D~和V~DS~之间的区别。
s参数数据用于“Vds = 3V，Id = 60 mA”，查看数据文件，您将在注释中看到。
每个器件的V~D~可能不是3V。
在这种情况下，对于2个器件，有效地串联连接，X2.V~D~将X1.V~DS~加到X2.V~DS~，即3V + 3V等6V。
您必须考虑每个器件的电压差，而不是直接通过DC分析产生的绝对电压。
然后，您需要调整每个器件的偏置，以根据需要在器件之间获得正确的电压差。



     以下为原文

  > {quote:title=nimbargi wrote:}{quote}
>             But I have taken ATF54143 3V,60mA transistor. As I said earlier at drain of X1  , I am getting 89.2mv and 59.8mA. Similarly I am getting  at the  drain of X2 voltage and current is 3v, 59.8mA. 
>            Is it o.k  voltage at the X1 of drain(89.2mV)(will it this much less voltage transistor work?), or otherwise we have to get the 3v also at the drain of X1, because we have taken 3v,60mA ATF54143 transistor.

You obviously do not understand the difference between V ~D~ and V ~DS~. The s-parameter data is for "Vds=3V, Id=60 mA", look in the data file and you will see that in the comment. V ~D~ may not be 3V for every device. In this case for the 2 devices, effectively connected in series, X2.V ~D~ would be X1.V ~DS~ added to X2.V ~DS~, i.e. 3V + 3V and so  6V. You have to be considering the voltage difference across each device and NOT the absolute voltage generated by the DC analysis directly. You then need to adjust the bias to each device to get the correct voltage difference across the devices as required.

> {quote：title = sdgrant写道：} {quote}>> {quote} >>>>>>你显然不明白V~D~和V~DS~之间的区别。
s参数数据用于“Vds = 3V，Id = 60 mA”，查看数据文件，您将在注释中看到。
每个器件的V~D~可能不是3V。
在这种情况下，对于2个器件，有效地串联连接，X2.V~D~将X1.V~DS~加到X2.V~DS~，即3V + 3V等6V。
您必须考虑每个器件的电压差，而不是直接通过DC分析产生的绝对电压。
然后，您需要调整每个器件的偏置，以根据需要在器件之间获得正确的电压差。
sdgrant先生，我很抱歉先生，我真的不明白，我必须做什么。
在晶体管的X1和X2的漏极处应该得到什么电压和电流，我如何在X1和X2的漏极处获得所需的电压和电流。我完全感到困惑，并且不能正确理解，我必须做什么。
我认为最初在每个器件晶体管的漏极，需要得到3v和60mA。
现在我很困惑每个设备的漏极电压和电流应该是多少。



     以下为原文

  > {quote:title=sdgrant wrote:}{quote}
> > {quote}
> >             > >           
> 
> You obviously do not understand the difference between V ~D~ and V ~DS~. The s-parameter data is for "Vds=3V, Id=60 mA", look in the data file and you will see that in the comment. V ~D~ may not be 3V for every device. In this case for the 2 devices, effectively connected in series, X2.V ~D~ would be X1.V ~DS~ added to X2.V ~DS~, i.e. 3V + 3V and so  6V. You have to be considering the voltage difference across each device and NOT the absolute voltage generated by the DC analysis directly. You then need to adjust the bias to each device to get the correct voltage difference across the devices as required.
sdgrant Sir,
                I am sorry sir, really I didn't understand , what I have to do .  What  voltage and current should get at drain of X1 and X2 of the transistors,how I have to get desired voltages and current at drains of the X1 and X2.I am totally confused and didn't understand properly, what I have to do.I thought that initially  at the drains of each device transistors , need to get 3v and 60mA. Now I am confused what  voltage and current should get at the drains of each device.

> {quote：title = nimbargi写道：} {quote}>我认为最初在每个器件晶体管的漏极，需要得到3v和60mA。
您希望每个晶体管的*漏极和源极*之间的电压差*为3V。
这是你需要考虑的。
不要只看漏极和栅极电压到电路接地。
您需要查看每个晶体管的漏极 - 源极和栅极 - 酸性电压。
然后，您还将看到3V电源电压出了什么问题。
从参考中的初始原理图开始，并考虑栅极，漏极，源节点处的节点电压。



     以下为原文

  > {quote:title=nimbargi wrote:}{quote}
> I thought that initially  at the drains of each device transistors , need to get 3v and 60mA. 

You want a *voltage difference* of 3V between the *drain and source* of each transistor. This is what you need to think about. Don't just look at the drain and gate voltages to circuit ground. You need to look at drain-source and gate-sourve voltages for each transtistor. Then, you will also see what is wrong with your 3V supply voltage.

Start with your initial schematic from your reference, and think about node voltages at the gate, drain, source nodes.

我会放弃。
最后一个提示：您不能将两个晶体管连接到相同的栅极电压。
对于60mA漏极电流，栅极电压必须比酸性电压高约0.6V。
X1的源电压为0V，因此需要X1栅极电压0.6V。
如果X1的漏 - 源电压为3V，则X2源电压为3V（X1漏极连接到X2源！），因此X2需要栅极电压3V + 0.6V = 3.6V。
当然，您需要3V + 3V = 6V电源电压。



     以下为原文

  I'll give up. 

One final last hint: You can't just connect both transistors to the same gate voltage.

For 60mA drain current, the gate voltage must be ~0.6V higher than the sourve voltage. 
X1 has source voltage of 0V, so you need X1 gate voltage 0.6V.
If the drain-source voltage of X1 is 3V, then X2 source voltage is 3V (X1 drain connected to X2 source!), so you need gate voltage 3V + 0.6V = 3.6V for X2.
And of course, you need 3V + 3V = 6V supply voltage.