VHDL中可以将两个长度不相同的数字相乘吗？

你好，
我正在研究一个VHDL项目，我需要将两个数字相乘，M1 et M2。
M1在8位上定义为带符号的定点数：“0 0.000000”
M2是16位有符号整数“0 000000000000000”
从数学上讲，乘法的答案应编码为24位（“0 00000000000000000000000”）
在VHDL中，我们可以将两个长度不相同的数字相乘吗？
如果没有，我们必须用符号位扩展最小值。
M1'
它会产生32位的乘法结果（M1'xM2），但24个足以编码“真实”结果......
因此，我试过：
Res：std_logic_vector（23 downto 0）;
...
RES
但在这种情况下，我在合成中发出警告，告诉我有一个长度不匹配...
然后我写道：
实体Synchro_voies是
港口 （
Clk：在std_logic中;
拉兹：在std_logic;
M1：在std_logic_vector（15 downto 0）;
M2：在std_logic_vector（7 downto 0）;
Res：在std_logic_vector（23 downto 0）
）;
结束Synchro_voies;
建筑行为的Synchro_voies是
信号Res1：std_logic_vector（31 downto 0）;
开始
Res'0'）;
elsif Clk'event和Clk ='1'然后
RES1
但在这种情况下，Res1注册人是强制/有用的???
亚历克斯



以下为原文

Hello,

I am working on a VHDL project, in which i need to multiply two numbers, M1 et  M2.

M1 is defined on 8 bits as a signed fixed point number : "0 0.000000"
M2 is a 16 bits signed integer "0 000000000000000"

Mathematically speaking the answer of the multiplication should be coded on 24 bit ("0 00000000000000000000000")

In VHDL, can we multiply two numbers that do not have the same length?

If not, we must then extend the smallest with its sign bit.
M1' <= (M1(7)& M1(7)& M1(7)& M1(7)& M1(7)& M1(7)& M1(7)& M1(7)&M1);
  
It induces a multiplication result (M1'xM2) of 32 bits but 24 are enough to code the "real" resul...

Therefore, i tried that :

Res : std_logic_vector ( 23 downto 0); ...Res <=  ((M1(7)& M1(7)& M1(7)& M1(7)& M1(7)& M1(7)& M1(7)& M1(7)&M1))*M2;

But in this case, i have warning in the synthesys, telling that i have a lenght missmatch...

I then wrote that :


entity Synchro_voies is   PORT (       Clk      :in std_logic;               Raz  :   in std_logic;       M1:instd_logic_vector (15 downto 0);       M2:instd_logic_vector (7 downto 0);       Res:instd_logic_vector (23 downto 0));end Synchro_voies;architecture Behavioral of Synchro_voies issignal Res1: std_logic_vector (31 downto 0);beginRes <= Res1 (23 downto 0);Phase_treat : process (Clk, RAZ)beginif Raz = '1' then     Res1 <= (others => '0');elsif Clk'event and Clk = '1' then     Res1 <= ((M2(7)&M2(7)&M2(7)&M2(7)&M2(7)&M2(7)&M2(7)&M2(7)&M2)*M1);end if;end process;end Behavioral;

But in this case, is the Res1 registrer mandatory/usefull???



Alex