移位寄存器的输出与时钟不对齐

你好，
对我来说这似乎是一个相当奇怪的问题。
我使用的是基于RAM的可变长度移位寄存器（附带.xco和.vhd文件），它具有通常的输入，输出，时钟和sclr端口。
当我在ModelSim中模拟这个模型时，我看到输出没有与时钟对齐：它出现在从时钟信号的下降沿延迟一段时间之后。
该延迟甚至不是时钟周期的整数倍。
奇怪的是，这个问题不会出现在基于RAM的移位寄存器的另一个模拟中，该移位寄存器的深度（比如说，16个字）比当前的移位寄存器（= 1024个字）更小。
我正在使用Xilinx ISE 11.4并在Virtex 5 SXT95上设计我的设计。
那么这里可能出现什么问题？
任何帮助将不胜感激。
问候，
Kumar Vijay Mishra。
shift_dly_files.zip 3 KB



以下为原文

Hello,

It appears a rather strange problem to me. I am using a variable-length RAM-based shift register (.xco and .vhd files attached) which has the usual input, output, clock and sclr ports. When I simulate this model in ModelSim, I see that the output is not aligned with the clock: It appears after some delay from the riding edge of the clock signal. This delay is not even some integer multiple of clock periods. Curiously, this problem doesn;t occur in another simulation of a RAM-based shift register which is of smaller depths (say, 16 words) than the current one (= 1024 words).

I am using Xilinx ISE 11.4 and targeting my design on Virtex 5 SXT95.

So what could be going wrong here? Any help would be greatly appreciated.

Regards,

Kumar Vijay Mishra.
            shift_dly_files.zip ‏3 KB