连接其他IC的任何良好实践技巧？

嗨马修，
如果FPGA旨在替代原始芯片，那么可能有计算机时钟信号可用。
如果可以将其与其中一个FPGA时钟输入连接，则可以使用3 MHZ进行保存，并忽略来自其他源的100 MHz（开头）。
这样，由计算机访问的控制寄存器组的行为类似于原始芯片。
如果功能非常简单，您可以在3 MHz处完成所有操作。
（原始芯片也必须处理它）
如果要实现一些需要更高时钟速度的改进，可以使用100MHz时钟并进行一些内部同步。
如果适用，最简单的方法是使用小型双端口RAM。
或者您在两个时钟域的边界放置了小移位寄存器级。
你在这个论坛上找到了很多解释如何做到这一点。
只是搜索一下。
有一个很好的综合 
Eilert



以下为原文

Hi Matthew,if the FPGA is intended to teplace the original chip, there's probably the computers Clock signal available.If it is possible to connect it with one of the FPGAs Clock inputs, you can savely work with the 3 MHZ and ignore the 100 MHz that come from another source (for the beginning).This way the controll register bank, that's accessed by the computer, behaves like the original chip.If the function is quite simple, you can probably do everything at 3 MHz. (The original chip had to deal with it as well)If you are going to implement some improvements that require higher clock speeds, you can use the 100MHz clock for that and do some internal synchronisation. Most simple approach, if applicable, is the use of a small dual port RAM.Or you put small shift register stages at the border of the two clock domains. You find a lot of explanations how to do it in this forum. Just search a little.   Have a nice synthesis  Eilert

谢谢（你的）信息！
在我发布我的初始问题之后，我实现了一个过滤器，它将两个主要的启用输入采样约原始系统时钟的1/4。
在这样做之后，令人难以置信的是整个赛道生机勃勃并且“完美地”工作！
我还是很震惊。
我已经超过两周没有进行FPGA工作了，我没想到事情会如此迅速地发挥作用。
我很高兴，但仍然感到惊讶。
由于某些原因，我无法使用原始系统时钟。
首先是因为原始芯片是异步的并且不使用系统时钟，它是通过来自主CPU的读和写使能信号驱动的。
另外，正如您所提到的，一旦我重现了原始芯片的所有功能，我就会计划一些可以从更快的时钟中受益的增强功能。
马修



以下为原文

Thanks for the info!  After I posted my initial question I implemented a filter that samples the two main enable inputs by about 1/4 of the original system's clock.  After doing that, unbelievably the whole circuit sprung to life and worked "perfectly"!!  I'm still in shock.  I have not been doing FPGA work for more than about two weeks and I did not expect things to work out so quickly.  I'm happy, but still amazed.
 
I can't use the original system clock for a few reasons.  First is because the original chip is asynchronous and does not use the system clock, it is driven via read and write enable signals from the main CPU.  Also, as you mentioned, once I reproduce all the functionality of the original chip, I'm planning on some enhancements that will benefit from the faster clock.
 
Matthew
 

嗨马修，
很高兴听到这个好消息。
如果外部电路没有时钟工作，你应该注意你正在处理的异步输入。
幸运的是，一切都很好，但请检查您的设计是否可以从亚稳态中解脱出来。
这很简单：在每个异步输入前面放一个小的移位寄存器（2..3 FF）。
也许它已经在您的输入滤波器电路中，然后您就完成了并且可以继续工作。
顺便说一下：无时钟电脑？
什么东西像霍尼韦尔或DEC机器从回来的时候？
有一个很好的综合 
Eilert



以下为原文

Hi Matthew,happy to hear this good news.If the external circuit works without clock, you should pay some attention to the asynchronous inputs you are dealing with.With some luck everything is just OK, but please check your design to be save from metastability. It's simple: Put a small Shift register (2..3 FFs) in front of every asynchronous input.Maybe it's already in your input-filter-circuit, then you are done and can work on.Btw: Clockless Computer? Something like a  Honeywell or DEC machine from way back when?Have a nice synthesis  Eilert

嘿艾勒特，
移位寄存器正是使一切工作的解决方案。
由于主机系统约为3MHz且FPGA为100MHz，因此我有一个8位移位寄存器，在FPGA时钟中约为70ns至80ns，因此大约是主机时钟的1/4。
它现在运作得很好。
主机系统是一台TI-99 / 4A家用电脑（我是一个经典的计算机家伙），我正在复制9918A VDP（视频数据处理器），因为有一些我一直想要但从未在99 /上的视频模式
4A。
:-)无论如何，9918A有自己的时钟，因为它必须生成视频信号并刷新其用于生成显示的动态RAM。
主系统通过两个主要输入与9918A通信，即csw和csr（写和读使能信号）。
因此，当CPU断言csw或csr时，9918A将通过向RAM写入数据或从RAM读取数据，设置内部寄存器等来响应.9918A没有任何定时信号返回主机CPU（仅8-
位数据总线和vsync中断信号），因此主机必须确保它等待必要的时间。
基本上csw和csr运行通信，我直接使用这些信号，非常像SRAM。
一旦我缓冲（过滤？）csw和csr输入，事情就很好了。
还有另外两个输入，“模式”输入和来自/到CPU的数据。
但是，模式和数据与csw和csr输入一起使用，由于我通过移位寄存器延迟csw和csr，因此在我使用它们时模式和数据应该是稳定的。
或者，我是否应该继续缓冲这些输入？
马修



以下为原文

Hey Eilert,
 
The shift register is exactly the solution that made everything work.  Since the host system is about 3MHz and the FPGA is 100MHz, I have an 8-bit shift register which is about 70ns to 80ns in FPGA clocks, so about 1/4 of the host clock.  It works very well now.
 
The host system is a TI-99/4A home computer (I'm a classic computer guy) and I'm reproducing the 9918A VDP (video data processor) since there are some video modes I always wanted but never had on the 99/4A. :-)  Anyway, the 9918A has its own clock since it has to generate the video signals and refresh its dynamic RAM that it uses to generate the display.
 
The main system communicates with the 9918A via two main inputs, a csw and csr (write and read enable signals).  So, when the CPU asserts either csw or csr, the 9918A will respond by writing or reading data to / from its RAM, setting internal registers, etc.  The 9918A does not have any timing signals back to the host CPU (only an 8-bit data bus and a vsync interrupt signal), so the host must ensure it waits the necessary amount of time.  Bascially the csw and csr run the communication and I was using those signals directly, very much like an SRAM.  Once I buffered (filtered?) the csw and csr inputs, things worked great.
 
There are also two other inputs, a "mode" input and the data from / to the CPU.  However, the mode and data are used in conjunction with the csw and csr inputs, and since I am delaying the csw and csr via the shift registers, the mode and data should be stable by the time I use them.  Or, should I go ahead and buffer those inputs as well?
 
Matthew
 

您可能会发现许多有趣的白皮书。
http://www.xilinx.com/support/documentation/white_papers/wp231.pdf（加速设计性能的HDL编码实践）http://www.xilinx.com/cn/support/documentation/white_papers/wp272.pdf（Get Smart
关于重置：思考本地，而非全球）http://www.xilinx.com/support/documentation/white_papers/wp275.pdf（确保您的优先级 - 使您的设计小50％）
http://www.xilinx.com/support/documentation/white_papers/wp361.pdf（维护可重复的结果）
除此之外：
http://www.xilinx.com/products/quality/fpga_best_practices.htm(FPGA设计最佳实践）
干杯，
BT



以下为原文

嗨马修，
是的，我记得TI 99 / 4A。
我的一个朋友曾经拥有一个。
（我的某个地方还有备用电源。）
为了抑制亚稳态效应，2或3个FF就足够了。
我不太了解你的设计，告诉你是否需要8个FF。
也许在你的设计中需要一些与它结合的功能。
（我只想到3 MHz信号的上升时间。
当采用100 MHz采样时，8个FF确实是一个不错的选择。）
在模式信号的情况下，我认为它是保存的，因为它们的行为连接到控制信号并接管到FPGA，只有在这些位稳定时才会发生FF。
因此，您希望改善TI的视频功能。
首先重新发明9918A然后改进已经是一些不错的工作。
您是否考虑过将整个TI99 / 4A放入FPGA中？
因为当机械部件（键盘，连接器）发生故障时，有些人可以选择使用标准部件进行更换。
（更不用说可能的性能改进等）
有一个很好的综合 
Eilert



以下为原文

Hi Matthew,Yes, I remember the TI 99/4A. A friend of mine once owned one. (I still have a spare power supply for it somewhere.)For suppressing metastability effects 2 or 3 FFs are sufficient. I  don't know enough about your design to tell wether you need the 8 FFs or not. Maybe there's some function combined with it that's needed in your design.(I'm just thinking about the rise times of the 3 MHz signals. When sampled with 100 MHz the 8 FFs may be a good choice indeed.)In the case of the Mode signals I think it's save, since their behavior is connected to the controll signals and takeover into FPGAs FFs only happens when these bits are stable. So, you want to improve the video capabilities of your TI. First reinventing the 9918A and then improving is already some nice work.Have you thought about putting the whole TI99/4A into a FPGA?  Because somewhen the mechanical parts (Keyboard, connectors) will fail, and then it's nice to have an option to use standard parts for replacement. (Not to mention possible performance improvements etc.)Have a nice synthesis  Eilert

timpe：谢谢你的链接，我马上就检查一下。
eilert：感谢您的反馈。
由于我添加了8个FF样本，因此CPU I / O工作得非常好。
现在我正在努力与视频生成，但我最终会得到它。
我已经想过一个完整的99 / 4A芯片，但我想一次开始一件。
此外，有很多99 / 4A用户喜欢真正的硬件和插入VGA显示器而不是电视会很好。
无论如何，我正在计划完成一个完整的SoC，但是直到我通过腰带获得VHDL，我可能会一次坚持使用一个。
马修



以下为原文

timpe: Thank you for the links, I'll check those out right away.
 
eilert: Thanks for the feedback.  The CPU I/O is working very nice since I added the 8 FF sample.  Now I'm struggling with the video generation, but I'll get it eventually.  I have thought about a complete 99/4A on a chip, but I want to start one piece at a time.  Also, there are a lot of 99/4A users who like the real hardware and plugging in a VGA monitor instead of a TV would be nice.  At any rate, I'm planning on working towards a complete SoC, but until I get VHDL under by belt I'm probably going to stick with one piece at a time.
 
Matthew