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我似乎无法破译tiM1寄存器以获得类似于TIM2或TIM4的基本定时器功能。仅在达到自动重载周期时才计数UP和中断。在我的应用程序中,我在达到周期之前将计数器重置为0,因此定时器中断是各种故障。当我将计数器设置为0时,TIM1会产生中断。有没有办法禁止更新中断的那部分?没有和输出可以使用比较吗?
目前我使用提供的标准库,下面的目的是让计时器平等运行: TIM1_TimeBaseInit(0x0020,TIM1_COUNTERMODE_UP,0x00B4,1); / *启用TIM1 IT UPDATE * / TIM1_ITConfig(TIM1_IT_UPDATE,ENABLE); / *启用TIM1 * / // TIM1_Cmd(ENABLE); // TIM2_DeInit(); / *时基配置* / TIM2_TimeBaseInit(TIM2_PRESCALER_64,0x00B4); / *启用TIM2 IT UPDATE * / TIM2_ITConfig(TIM2_IT_UPDATE,ENABLE); / *启用TIM2 * / // TIM2_Cmd(ENABLE); // TIM4_DeInit(); / *时基配置* / TIM4_TimeBaseInit(TIM4_PRESCALER_64,0xB4); / *启用TIM4 IT UPDATE * / TIM4_ITConfig(TIM4_IT_UPDATE,ENABLE); 谢谢约翰 #TIM1-STM8S 以上来自于谷歌翻译 以下为原文 I cant seem to decipher the TIM1 registers to get a basic timer function similar to TIM2 or TIM4. Count UP and interrupt only if you reach the auto-reload period. In my application I reset the counter to 0 before the period is reached so a timer interrupt is a fault of sorts. TIM1 generates an interrupt when I set the counter to 0. Is there a way to inhibit that portion of the update interrupt? Can a compare be used without and output? currently I use the standard library provided and the intent below was to have the timers operate equally: TIM1_TimeBaseInit(0x0020, TIM1_COUNTERMODE_UP, 0x00B4, 1 ); /* Enable TIM1 IT UPDATE */ TIM1_ITConfig( TIM1_IT_UPDATE, ENABLE); /* Enable TIM1 */ // TIM1_Cmd(ENABLE); // TIM2_DeInit(); /* Time base configuration */ TIM2_TimeBaseInit(TIM2_PRESCALER_64, 0x00B4 ); /* Enable TIM2 IT UPDATE */ TIM2_ITConfig(TIM2_IT_UPDATE, ENABLE); /* Enable TIM2 */ // TIM2_Cmd(ENABLE); // TIM4_DeInit(); /* Time base configuration */ TIM4_TimeBaseInit(TIM4_PRESCALER_64, 0xB4 ); /* Enable TIM4 IT UPDATE */ TIM4_ITConfig(TIM4_IT_UPDATE, ENABLE); Thanks John #tim1-stm8s |
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我发现用软件直接写入计数器寄存器而不产生中断是不可能的。但是我可以使用以下方法将计数器重置为0:
TIM1-> CR1 | =(uint8_t)(TIM1_CR1_UDIS); TIM1-> EGR | =(uint8_t)(TIM1_EGR_UG); TIM1-> CR1& =(uint8_t)(~TIM1_CR1_UDIS); 用UDIS关闭UIF标志的设置,然后复位计数器(和其他影子寄存器),然后重新使能UIF标志,这样如果定时器变为OFF,你将得到溢出/下溢中断。 该手册建议只设置CR1寄存器的URS位将仅启用上溢/下溢中断,但这似乎不起作用。当我向计数器写0时,我仍然有interruopts。 约翰 以上来自于谷歌翻译 以下为原文 I've found it impossible to directly write to the counter register with software without generating an interrupt. However I can reset the counter to 0 using the following: TIM1->CR1 |= (uint8_t)(TIM1_CR1_UDIS); TIM1->EGR |= (uint8_t)(TIM1_EGR_UG); TIM1->CR1 &= (uint8_t)(~TIM1_CR1_UDIS); Turn OFF the setting of the UIF flag with UDIS then reset the counters (and other shadow registers) and then re-enable the UIF flag so that if the timer goes OFF you will get the overflow/underflow interrupt. The manual suggests that just setting the URS bit of the CR1 register will enable ONLY the over/underflow interrupt but that didn't seems to work. I still got interruopts when I write a 0 to the counter. John |
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