CAN通信控制的位时序逻辑--Bit Timing Logic具体实现

2018-12-20 11:40:50 3279 CAN通信 CAN 时序

0 位时序逻辑实现 CAN 总线协议中对位同步的有关控制。位时序逻辑监视串行 CAN 总线并处理与总线相关的位时序。它在报文开始发送、总线电平从隐性值跳变到显性值时同步于 CAN总线上的位数据流（硬同步），并在该报文的传送过程中，每遇到一次从隐性值到显性值的跳变沿就进行一次重同步（软同步）。位时序逻辑还提供可编程的时间段来补偿传播延迟时间和相位漂移。主要程序代码如下： //计数器 always @ (posedge clk or posedge rst) begin if (rst) clk_cnt <= 0; else if (clk_cnt == (preset_cnt-1)) clk_cnt <=#Tp 0; else clk_cnt <=#Tp clk_cnt + 1; end //产生定义波特率的一般使能信号 always @ (posedge clk or posedge rst) begin if (rst) clk_en <= 1'b0; else if (clk_cnt == (preset_cnt-1)) clk_en <=#Tp 1'b1; else clk_en <=#Tp 1'b0; end //改变状态 assign go_sync = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt == time_segment2))); assign go_seg1 = clk_en & (sync \| hard_sync \| (resync & seg2 & sync_window) \| (resync_latched & sync_window)); assign go_seg2 = clk_en & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay))); //当探测到 SJW 字段的沿时，同步请求被锁存并被执行 always @ (posedge clk or posedge rst) begin if (rst) resync_latched <= 1'b0; else if (resync & seg2 & (~sync_window)) resync_latched <=#Tp 1'b1; else if (go_seg1) resync_latched <= 1'b0; end //同步的平台或片断 always @ (posedge clk or posedge rst) begin if (rst) sync <= 0; else if (go_sync) sync <=#Tp 1'b1; else if (go_seg1) sync <=#Tp 1'b0; end assign tx_point = go_sync; //片断 seg1 always @ (posedge clk or posedge rst) begin if (rst) seg1 <= 1; else if (go_seg1) seg1 <=#Tp 1'b1; else if (go_seg2) seg1 <=#Tp 1'b0; end //片断 seg2 always @ (posedge clk or posedge rst) begin if (rst) seg2 <= 0; else if (go_seg2) seg2 <=#Tp 1'b1; else if (go_sync \| go_seg1) seg2 <=#Tp 1'b0; end //Quant 计数器 always @ (posedge clk or posedge rst) begin if (rst) quant_cnt <= 0; else if (go_sync \| go_seg1 \| go_seg2) quant_cnt <=#Tp 0; else if (clk_en) quant_cnt <=#Tp quant_cnt + 1'b1; end //当探测到后沿时，片断 seg1 被延时 begin if (rst) delay <= 0; else if (clk_en & resync & seg1) delay <=#Tp (quant_cnt > sync_jump_width)? (sync_jump_width + 1) : (quant_cnt + 1); else if (go_sync \| go_seg1) delay <=#Tp 0; end //如果沿出现在这个窗口中，相位的错误将得到完全的补偿 assign sync_window = ((time_segment2 - quant_cnt) < ( sync_jump_width + 1)); //数据采样 always @ (posedge clk or posedge rst) begin if (rst) sample <= 2'b11; else if (clk_en) sample <= {sample[0], rx}; end //获得使能后，采样完成 always @ (posedge clk or posedge rst) begin if (rst) begin sampled_bit <= 1; sampled_bit_q <= 1; sample_point <= 0; end else if (clk_en & (~hard_sync)) begin if (seg1 & (quant_cnt == (time_segment1 + delay))) begin sample_point <=#Tp 1; sampled_bit_q <=#Tp sampled_bit; if (triple_sampling) sampled_bit <=#Tp (sample[0] & sample[1]) \| ( sample[0] & rx) \| (sample[1] & rx); else sampled_bit <=#Tp rx; end end else sample_point <=#Tp 0; end //阻塞同步 always @ (posedge clk or posedge rst) begin if (rst) sync_blocked <=#Tp 1'b0; else if (clk_en) begin if (hard_sync \| resync) sync_blocked <=#Tp 1'b1; else if (seg2 & quant_cnt == time_segment2) sync_blocked <=#Tp 1'b0; end end //阻塞重同步直到收到开始信号 /* Blocking resynchronization until reception starts (needed because after reset mode exits we are waiting for end-of-frame and interframe. No resynchronization is needed meanwhile). / always @ (posedge clk or posedge rst) begin if (rst) resync_blocked <=#Tp 1'b1; else if (reset_mode) resync_blocked <=#Tp 1'b1; else if (hard_sync) resync_blocked <=#Tp 1'b0; end 复制代码* 0
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