CAN通信寄存器控制的具体实现

2018-12-20 11:34:59 2264 CAN通信 CAN 寄存器

0 这个模块用于完成程序中所有有关寄存器的操作，代码如下： always @ (posedge clk) begin tx_successful_q <=#Tp tx_successful; overrun_q <=#Tp overrun; transmit_buffer_status_q <=#Tp transmit_buffer_status; info_empty_q <=#Tp info_empty; error_status_q <=#Tp error_status; node_bus_off_q <=#Tp node_bus_off; node_error_passive_q <=#Tp node_error_passive; end … //模式寄存器 wire [0:0] mode; wire [4:1] mode_basic; wire [3:1] mode_ext; wire receive_irq_en_basic; wire transmit_irq_en_basic; wire error_irq_en_basic; wire overrun_irq_en_basic; can_register_asyn_syn #(1, 1'h1) MODE_REG0 ( .data_in(data_in[0]), .data_out(mode[0]), .we(we_mode), .clk(clk), .rst(rst), .rst_sync(set_reset_mode) ); can_register_asyn #(4, 0) MODE_REG_BASIC ( .data_in(data_in[4:1]), .data_out(mode_basic[4:1]), .we(we_mode), .clk(clk), .rst(rst) ); can_register_asyn #(3, 0) MODE_REG_EXT ( .data_in(data_in[3:1]), .data_out(mode_ext[3:1]), .we(we_mode & reset_mode), .clk(clk), .rst(rst) ); //命令寄存器 wire [4:0] command; can_register_asyn_syn #(1, 1'h0) COMMAND_REG0 ( .data_in(data_in[0]), .data_out(command[0]), .we(we_command), .clk(clk), .rst(rst), .rst_sync(tx_request & sample_point) ); can_register_asyn_syn #(1, 1'h0) COMMAND_REG1 ( .data_in(data_in[1]), .data_out(command[1]), .we(we_command), .clk(clk), .rst(rst), .rst_sync(abort_tx & ~transmitting) ); can_register_asyn_syn #(2, 2'h0) COMMAND_REG ( .data_in(data_in[3:2]), .data_out(command[3:2]), .we(we_command), .clk(clk), .rst(rst), .rst_sync(\|command[3:2]) ); can_register_asyn_syn #(1, 1'h0) COMMAND_REG4 ( .data_in(data_in[4]), .data_out(command[4]), .we(we_command), .clk(clk), .rst(rst), .rst_sync(tx_successful & (~tx_successful_q) \| abort_tx) ); assign self_rx_request = command[4] & (~command[0]); assign clear_data_overrun = command[3]; assign release_buffer = command[2]; assign abort_tx = command[1] & (~command[0]) & (~command[4]); assign tx_request = command[0] \| command[4]; always @ (posedge clk or posedge rst) begin if (rst) single_shot_transmission <= 1'b0; else if (we_command & data_in[1] & (data_in[1] \| data_in[4])) single_shot_transmission <=#Tp 1'b1; else if (tx_successful & (~tx_successful_q)) single_shot_transmission <=#Tp 1'b0; end //状态寄存器 wire [7:0] status; assign status[7] = node_bus_off; assign status[6] = error_status; assign status[5] = transmit_status; assign status[4] = receive_status; assign status[3] = transmission_complete; assign status[2] = transmit_buffer_status; assign status[1] = overrun_status; assign status[0] = receive_buffer_status; always @ (posedge clk or posedge rst) begin if (rst) transmission_complete <= 1'b1; else if (tx_successful & (~tx_successful_q) \| abort_tx) transmission_complete <=#Tp 1'b1; else if (tx_request) transmission_complete <=#Tp 1'b0; end always @ (posedge clk or posedge rst) begin if (rst) transmit_buffer_status <= 1'b1; else if (tx_request) transmit_buffer_status <=#Tp 1'b0; else if (~need_to_tx) transmit_buffer_status <=#Tp 1'b1; end always @ (posedge clk or posedge rst) begin if (rst) overrun_status <= 1'b0; else if (overrun & (~overrun_q)) overrun_status <=#Tp 1'b1; else if (clear_data_overrun) overrun_status <=#Tp 1'b0; end always @ (posedge clk or posedge rst) begin if (rst) receive_buffer_status <= 1'b0; else if (release_buffer) receive_buffer_status <=#Tp 1'b0; else if (~info_empty) receive_buffer_status <=#Tp 1'b1; end //总线时序寄存器 1 wire [7:0] bus_timing_0; can_register #(8) BUS_TIMING_0_REG ( .data_in(data_in), .data_out(bus_timing_0), .we(we_bus_timing_0), .clk(clk) ); assign baud_r_presc = bus_timing_0[5:0]; assign sync_jump_width = bus_timing_0[7:6]; //总线时序寄存器 2 wire [7:0] bus_timing_1; can_register #(8) BUS_TIMING_1_REG ( .data_in(data_in), .data_out(bus_timing_1), .we(we_bus_timing_1), .clk(clk) ); assign time_segment1 = bus_timing_1[3:0]; assign time_segment2 = bus_timing_1[6:4]; assign triple_sampling = bus_timing_1[7]; //错误提示寄存器 can_register_asyn #(8, 96) ERROR_WARNING_REG ( .data_in(data_in), .data_out(error_warning_limit), .we(we_error_warning_limit), .clk(clk), .rst(rst) ); //时钟分频寄存器 wire [7:0] clock_divider; wire clock_off; wire [2:0] cd; reg [2:0] clkout_div; reg [2:0] clkout_cnt; reg clkout_tmp; //reg clkout; can_register #(1) CLOCK_DIVIDER_REG_7 ( .data_in(data_in[7]), .data_out(clock_divider[7]), .we(we_clock_divider_hi), .clk(clk) ); assign clock_divider[6:4] = 3'h0; can_register #(1) CLOCK_DIVIDER_REG_3 ( .data_in(data_in[3]), .data_out(clock_divider[3]), .we(we_clock_divider_hi), .clk(clk) ); can_register #(3) CLOCK_DIVIDER_REG_LOW ( .data_in(data_in[2:0]), .data_out(clock_divider[2:0]), .we(we_clock_divider_low), .clk(clk) ); assign extended_mode = clock_divider[7]; assign clock_off = clock_divider[3]; assign cd[2:0] = clock_divider[2:0]; always @ (cd) begin case (cd) // synopsys_full_case synopsys_paralel_case 3'b000 : clkout_div <= 0; 3'b001 : clkout_div <= 1; 3'b010 : clkout_div <= 2; 3'b011 : clkout_div <= 3; 3'b100 : clkout_div <= 4; 3'b101 : clkout_div <= 5; 3'b110 : clkout_div <= 6; 3'b111 : clkout_div <= 0; endcase end always @ (posedge clk or posedge rst) begin if (rst) clkout_cnt <= 3'h0; else if (clkout_cnt == clkout_div) clkout_cnt <=#Tp 3'h0; else clkout_cnt <= clkout_cnt + 1'b1; end always @ (posedge clk or posedge rst) begin if (rst) clkout_tmp <= 1'b0; else if (clkout_cnt == clkout_div) clkout_tmp <=#Tp ~clkout_tmp; end always @ (cd or clkout_tmp or clock_off) begin if (clock_off) clkout <=#Tp 1'b1; else clkout <=#Tp clkout_tmp; end assign clkout = clock_off ? 1'b1 : ((&cd)? clk : clkout_tmp); //从寄存器中读数据 always @ ( addr or read or extended_mode or mode or bus_timing_0 or bus_timing_1 or clock_divider or acceptance_code_0 or acceptance_code_1 or acceptance_code_2 or acceptance_code_3 or acceptance_mask_0 or acceptance_mask_1 or acceptance_mask_2 or acceptance_mask_3 or reset_mode or tx_data_0 or tx_data_1 or tx_data_2 or tx_data_3 or tx_data_4 or tx_data_5 or tx_data_6 or tx_data_7 or tx_data_8 or tx_data_9 or status or error_warning_limit or rx_err_cnt or tx_err_cnt or irq_en_ext or irq_reg or mode_ext or arbitration_lost_capture or rx_message_counter or mode_basic or error_capture_code ) begin if(read) // read begin if (extended_mode) // EXTENDED mode (Different register map depends on mode) begin case(addr) 8'd0 : data_out_tmp <= {4'b0000, mode_ext[3:1], mode[0]}; 8'd1 : data_out_tmp <= 8'h0; 8'd2 : data_out_tmp <= status; 8'd3 : data_out_tmp <= irq_reg; 8'd4 : data_out_tmp <= irq_en_ext; 8'd6 : data_out_tmp <= bus_timing_0; 8'd7 : data_out_tmp <= bus_timing_1; 8'd11 : data_out_tmp <= {3'h0, arbitration_lost_capture[4:0]}; 8'd12 : data_out_tmp <= error_capture_code; 8'd13 : data_out_tmp <= error_warning_limit; 8'd14 : data_out_tmp <= rx_err_cnt; 8'd15 : data_out_tmp <= tx_err_cnt; 8'd16 : data_out_tmp <= acceptance_code_0; 8'd17 : data_out_tmp <= acceptance_code_1; 8'd18 : data_out_tmp <= acceptance_code_2; 8'd19 : data_out_tmp <= acceptance_code_3; 8'd20 : data_out_tmp <= acceptance_mask_0; 8'd21 : data_out_tmp <= acceptance_mask_1; 8'd22 : data_out_tmp <= acceptance_mask_2; 8'd23 : data_out_tmp <= acceptance_mask_3; 8'd24 : data_out_tmp <= 8'h0; 8'd25 : data_out_tmp <= 8'h0; 8'd26 : data_out_tmp <= 8'h0; 8'd27 : data_out_tmp <= 8'h0; 8'd28 : data_out_tmp <= 8'h0; 8'd29 : data_out_tmp <= {1'b0, rx_message_counter}; 8'd31 : data_out_tmp <= clock_divider; default: data_out_tmp <= 8'h0; endcase end else // BASIC mode begin case(addr) 8'd0 : data_out_tmp <= {3'b001, mode_basic[4:1], mode[0]}; 8'd1 : data_out_tmp <= 8'hff; 8'd2 : data_out_tmp <= status; 8'd3 : data_out_tmp <= {4'hf, irq_reg[3:0]}; 8'd4 : data_out_tmp <= reset_mode? acceptance_code_0 : 8'hff; 8'd5 : data_out_tmp <= reset_mode? acceptance_mask_0 : 8'hff; 8'd6 : data_out_tmp <= reset_mode? bus_timing_0 : 8'hff; 8'd7 : data_out_tmp <= reset_mode? bus_timing_1 : 8'hff; 8'd10 : data_out_tmp <= reset_mode? 8'hff : tx_data_0; 8'd11 : data_out_tmp <= reset_mode? 8'hff : tx_data_1; 8'd12 : data_out_tmp <= reset_mode? 8'hff : tx_data_2; 8'd13 : data_out_tmp <= reset_mode? 8'hff : tx_data_3; 8'd14 : data_out_tmp <= reset_mode? 8'hff : tx_data_4; 8'd15 : data_out_tmp <= reset_mode? 8'hff : tx_data_5; 8'd16 : data_out_tmp <= reset_mode? 8'hff : tx_data_6; 8'd17 : data_out_tmp <= reset_mode? 8'hff : tx_data_7; 8'd18 : data_out_tmp <= reset_mode? 8'hff : tx_data_8; 8'd19 : data_out_tmp <= reset_mode? 8'hff : tx_data_9; 8'd31 : data_out_tmp <= clock_divider; default: data_out_tmp <= 8'h0; endcase end end else data_out_tmp <= 8'h0; end always @ (posedge clk or posedge rst) begin if (rst) data_out <= 0; else if (read) data_out <=#Tp data_out_tmp; end 复制代码 0
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