不同内核的外设性能是不同的吗

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     以下为原文
  Appreciate if someone shed lights on this.

不，外围设备本身不显示不同的行为或性能取决于它们与之交互的核心。CPU的电源模式不影响外围设备的性能，只要系统处于活动模式（即CPU中的至少一个不是处于休眠功率模式）。即使当两个CPU处于休眠模式时，外围设备仍然保持活动，并对其配置/性能起作用。
也就是说，M4和M0+使用不同的接口（而不是基础设施）来与外围设备（MMIO寄存器接口）交互。M4使用快速基础设施和M0+（和其他总线主机，如DMA，加密）使用缓慢的基础设施，以连接到外设。为了便于多主接口，在设备中提供仲裁器（选择要与之交谈的主接口）和桥接器（同步时钟到周边时钟域）。因此，您可以观察到一些（读取的‘预期’）性能降低（取决于在任何给定时间的活动总线主控器的数量）。
让我知道如果这有帮助，或者如果你需要进一步澄清。
当做，
Meenakshi Sundaram R



     以下为原文
  No, the peripherals as such do not show different behavior or performance depending on the core they are interacting with. The CPU's power mode does not impact the peripheral's performance as long as the system is in Active mode (i.e. at least one of the CPU is not in DeepSleep power mode). Even when both the CPUs are in Sleep mode, the peripherals remain active and function to their configuration/performance.
 
That said, M4 and M0+ use different interface (rather infrastructure) to interact with the peripherals (the MMIO register interface). M4 uses fast infrastructure and M0+ (and other bus masters like DMA, Crypto) use slow infrastructure for interfacing to the peripherals. In order to facilitate multiple master interface, arbiters (select the master interface to talk to) and bridges (sync's the clock to the peri clock domain) are provided in the device. Because of this you may observe some (read 'expected') performance reduction (depending on the number of active bus masters at any given time).
 
Let me know if this helps or if you need further clarification.
 
Regards,
Meenakshi Sundaram R