完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
你好,
该设计包括HDMI,DP和 SDI子系统。 视频phy控制器IP用于HDMI,DP收发器配置。 以下是一些警告, [Vivado 12-1411]不能设置端口LOC属性,实例i_design_1 / design_1_i / vid_phy_controller_1 /安装/ gt_wrapper_inst /安装/ gen_gtwizard_gthe4_top.design_1_vid_phy_controller_1_0_gtwrapper_gtwizard_gthe4_inst / gen_gtwizard_gthe4.gen_channel_container [2] .gen_enabled_channel.gthe4_channel_wrapper_inst / channel_inst / gthe4_channel_gen.gen_gthe4_channel_inst [0]。 GTHE4_CHANNEL_PRIM_INST不能被放置在现场的GTHE4_CHANNEL_X0Y4 GTHE4_CHANNEL因为BEL通过i_design_1 / design_1_i / vid_phy_controller_0 /安装/ gt_wrapper_inst /安装/ gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst / gen_gtwizard_gthe4.gen_channel_container [1] .gen_enabled_channel.gthe4_channel_wrapper_inst / channel_inst / gthe4_channel_gen.gen_gthe4_channel_inst [0占用 ] .GTHE4_CHANNEL_PRIM_INST(端口:)。 这可能是由于贝尔约束冲突引起的[“E:/project_1/project_1.srcs/constrs_1/imports/imports/sdi_ex_passthru_1l_zcu106.xdc”:82] [Vivado 12-1411]不能设置端口LOC属性,实例i_design_1 / design_1_i / vid_phy_controller_1 /安装/ gt_wrapper_inst /安装/ gen_gtwizard_gthe4_top.design_1_vid_phy_controller_1_0_gtwrapper_gtwizard_gthe4_inst / gen_gtwizard_gthe4.gen_channel_container [2] .gen_enabled_channel.gthe4_channel_wrapper_inst / channel_inst / gthe4_channel_gen.gen_gthe4_channel_inst [0]。 GTHE4_CHANNEL_PRIM_INST不能被放置在现场的GTHE4_CHANNEL_X0Y4 GTHE4_CHANNEL因为BEL通过i_design_1 / design_1_i / vid_phy_controller_0 /安装/ gt_wrapper_inst /安装/ gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst / gen_gtwizard_gthe4.gen_channel_container [1] .gen_enabled_channel.gthe4_channel_wrapper_inst / channel_inst / gthe4_channel_gen.gen_gthe4_channel_inst [0占用 ] .GTHE4_CHANNEL_PRIM_INST(端口:)。 这可能是由于贝尔约束冲突引起的[“E:/project_1/project_1.srcs/constrs_1/imports/imports/sdi_ex_passthru_1l_zcu106.xdc”:83] 这个关键警告可能是什么以及如何克服这个问题? 我相信在某些地方我给出的限制和Video Phy控制器IP生成的.xdc文件约束是相互矛盾的。 不过不确定。 之前有没有人遇到这个警告? 问候, Vinay Shenoy 以上来自于谷歌翻译 以下为原文 Hello, The design consists of HDMI, DP & SDI subsystems. Video phy controller IP is used for HDMI, DP transceiver configuration. Below are some of the warnings, [Vivado 12-1411] Cannot set LOC property of ports, Instance i_design_1/design_1_i/vid_phy_controller_1/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_1_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[2].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST can not be placed in GTHE4_CHANNEL of site GTHE4_CHANNEL_X0Y4 because the bel is occupied by i_design_1/design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST(port:). This could be caused by bel constraint conflict ["E:/project_1/project_1.srcs/constrs_1/imports/imports/sdi_ex_passthru_1l_zcu106.xdc":82] [Vivado 12-1411] Cannot set LOC property of ports, Instance i_design_1/design_1_i/vid_phy_controller_1/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_1_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[2].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST can not be placed in GTHE4_CHANNEL of site GTHE4_CHANNEL_X0Y4 because the bel is occupied by i_design_1/design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST(port:). This could be caused by bel constraint conflict ["E:/project_1/project_1.srcs/constrs_1/imports/imports/sdi_ex_passthru_1l_zcu106.xdc":83] What could be this critical warning indicating and how to overcome this? I believe somewhere the constraints what I give and the Video Phy controller IP generated .xdc file contraints are conflicting. Not sure though. Did anyone encounter this warning before? Regards, Vinay Shenoy |
|
相关推荐
1个回答
|
|
你好@ vinay_shenoy。
该消息意味着相互矛盾的约束。 对于使用收发器的大多数IP,以“LOC”约束的形式生成对GTHE4_CHANNEL的物理约束。 为了帮助放置位置,为GTHE4_CHANNEL逻辑创建了形状。 形状指定了GTHE4_CHANNEL,缓冲区和IO之间的相对位置。 因此,连接到GT的IO不需要受到约束,因为它们将通过来自IP的GTHE4_CHANNEL约束来约束。 如果您具有顶级IO约束,将GT置于不受IP约束定义的单独位置,则可以看到此警告。 我会尝试通过IP自定义调整IO和GTHE4_CHANNEL位置。 这通常允许选择放置GTHE4_CHANNEL的位置。 应在具有“_gt.xdc”后缀的IP XDC文件中找到约束。 您还可以通过写出当前约束(write_xdc)并搜索“GTHE4_CHANNEL”来找到它们。 -------------------------------------------------- -----------------------不要忘记回答,kudo,并接受为解决方案.------------- -------------------------------------------------- ---------- 以上来自于谷歌翻译 以下为原文 Hi @vinay_shenoy. The message would imply conflicting constraints. For most IPs using Transceivers, physical constraints on the GTHE4_CHANNELs are generated in the form of "LOC" constraints. To assist with placement placement shapes are created for the GTHE4_CHANNEL logic. The shape specifies relative placement between the GTHE4_CHANNEL, buffers, and IOs. Therefore, the IOs connected to the GT do not need to be constrained, as they will be constrained through the GTHE4_CHANNEL constraint from the IP. If you have top-level IO constraints that put the GT in a separate location than defined by the IP constraint, this warning can be seen. I would try to adjust the IO and GTHE4_CHANNEL location through the IP customization. This typically allows a choice as to where the GTHE4_CHANNEL is placed. The constraints should be found in an IP XDC file with the "_gt.xdc" suffix. You can also find these by writing out the current constraints (write_xdc), and searching for "GTHE4_CHANNEL". ------------------------------------------------------------------------- Don’t forget to reply, kudo, and accept as solution. ------------------------------------------------------------------------- |
|
|
|
只有小组成员才能发言,加入小组>>
2395 浏览 7 评论
2810 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2277 浏览 9 评论
3354 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2445 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
780浏览 1评论
请问vc707的电源线是如何连接的,我这边可能出现了缺失元件的情况导致无法供电
558浏览 1评论
求一块XILINX开发板KC705,VC707,KC105和KCU1500
405浏览 1评论
1985浏览 0评论
704浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-12-4 01:53 , Processed in 1.217735 second(s), Total 49, Slave 41 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号