完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
扫一扫,分享给好友
嗨,我正在寻找有关如何使用Xilinx Vivado创建Hard宏的示例。
了解如何在设计中修复路由并在阅读pdf(下面)时,提到可以根据要求提供示例,这将非常有帮助。 我是否可以收到一些此实施的示例?https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug905-vivado-hierarchical-design.pdf特别是我对Bottom up重用示例以及如何在 Vivado。您对此事的支持将受到高度赞赏。 以上来自于谷歌翻译 以下为原文 Hi, I am looking for examples on how to create Hard macro using Xilinx Vivado. It would be very helpful to learn how to fix routing in the design and upon reading the pdf (below) it was mentioned that examples are available upon request. Can I receive some examples for this implementation? https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug905-vivado-hierarchical-design.pdf Particularly I am interested in Bottom up reuse examples and how to implement this in Vivado. Your support regarding the matter would be highly appreciated. |
|
相关推荐
5个回答
|
|
@shehzeensh,
UG905中提到的文件出现在下面的教程中。 https://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_2/ug946-vivado-hierarchical-design-tutorial.pdf --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用,请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 @shehzeensh, The files mentioned in UG905 is present in the below tutorial. https://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_2/ug946-vivado-hierarchical-design-tutorial.pdf --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
|
|
|
您提供的链接与我发布的链接相同。
它提到示例文件可根据要求提供。 我正在请求示例文件。 它们可以在任何地方使用吗? 特别是,有没有关于修复路由的示例文件? 谢谢 以上来自于谷歌翻译 以下为原文 The link you have provided is the same as the link I have posted. It mentions that example files are available upon request. I am requesting the example files. Are they available at any location? Particularly, are there any example files on fixing routing? Thanks |
|
|
|
为了澄清,UG946文件(syedz上面链接的第5页)与UG905(上面的链接)中引用的示例设计文件相同。
关于Hard Macro,您应该看一下有关Vivado XDC Macro Creation的以下Quick take Vivado视频。 有关XDC宏命令的更多详细信息,请参阅“Vivado Design Suite Tcl命令参考指南”。 -------------------------------------------------- -----------------------不要忘记回答,kudo,并接受为解决方案.------------- -------------------------------------------------- ---------- 以上来自于谷歌翻译 以下为原文 Just to clarify, the UG946 files (page 5 of syedz's above link) are the same example design files that are referenced in UG905 (your link above). Regarding Hard Macro, you should have a look at the following Quick take Vivado video regarding Vivado XDC Macro Creation. Further details on the XDC macros commands can be found in the Vivado Design Suite Tcl Command Reference Guide. ------------------------------------------------------------------------- Don’t forget to reply, kudo, and accept as solution. ------------------------------------------------------------------------- |
|
|
|
谢谢你的帮助。我成功地创建了Macro但是在使用它时遇到了麻烦。
Myquestion现在是关于宏实例化的。 我们如何在创建后多次使用同一个宏,保持宏内部元素的相同位置和路由? 我们正在尝试遵循此文档:https://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_1/ug903-vivado-using-constraints.pdf 在页129,“管理宏示例二” 如果每个单元格包含一个宏,我会感到困惑,或者此示例仅在其中一个实例中创建一个宏。 我也对这个例子中的u0感到困惑。 我也来了:http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug986-vivado-tutorial-implementation.pdf 这个posthttps://forums.xilinx.com/t5/Inmplementation/hard-macro-in-vivado/m-p/519417 但我想了解路由在Vivado中的工作原理。 例如,如果有相同宏的8个实例,我们需要8个xdc文件吗? 该文档要求使用固定路由,但如果我们有8个单独的xdc文件,我们如何确保所有这些文件的路由相同? 我们应该将固定路由属性应用于哪个组件? 您对此事的帮助将受到高度赞赏。 以上来自于谷歌翻译 以下为原文 Thank you for your help. I was successfully able to create Macro but am having trouble using it. My question now is about macro instantiation. How can we use the same macro multiple times after the creation, maintaining the same relative location and routing of the elements inside the Macro? We are trying to follow this document: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_1/ug903-vivado-using-constraints.pdf On page 129, 'Managing Macros Example Two' I am confused if each cell contains a macro, or this example creates a macro in only one of the instances. I am also confused about what u0 is in this example. I also came across https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug986-vivado-tutorial-implementation.pdf and this post https://forums.xilinx.com/t5/Implementation/hard-macro-in-vivado/m-p/519417 but am trying to understand how routing works in Vivado. For example, if there are 8 instances of the same macro, do we need 8 xdc files? The document asked to use fixed routing but if we have 8 separate xdc files how do we make sure the routing is same across all of them? To which component do we apply the fixed routing property? Your help regarding the matter would be highly appreciated. |
|
|
|
@shehzeensh,
查看此视频,其中包含有关将多个实例应用于同一XDC宏模式的信息。 https://www.xilinx.com/video/hardware/vivado-xdc-macro-creation.html --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用,请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 @shehzeensh, Check this video which has information on applying same XDC macro pattern to multiple instances. https://www.xilinx.com/video/hardware/vivado-xdc-macro-creation.html --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
|
|
|
只有小组成员才能发言,加入小组>>
2361 浏览 7 评论
2780 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2247 浏览 9 评论
3324 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2414 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
730浏览 1评论
请问vc707的电源线是如何连接的,我这边可能出现了缺失元件的情况导致无法供电
524浏览 1评论
求一块XILINX开发板KC705,VC707,KC105和KCU1500
336浏览 1评论
742浏览 0评论
1935浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-11-9 05:34 , Processed in 1.205174 second(s), Total 85, Slave 68 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号