完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
我试图设置引脚oledrgb和wifi模块而不是专用插槽,所以我把它们设置为外部并设置xdc文件,但问题是由于某种原因它给了我错误。
[放置30-58] IO放置是不可行的。 未放置的终端数量(16)大于可用站点数量(0)。以下是具有可用引脚的存储区:IO组:0用于:SioStd:LVCMOS18 VCCO = 1.8终止:0 TermDir:BiDi RangeId:1 Drv:12 只有0点的设备可用,但需要16 sites.Term:PmodOLEDrgb_out_0_pin10_ioTerm:PmodOLEDrgb_out_0_pin1_ioTerm:PmodOLEDrgb_out_0_pin2_ioTerm:PmodOLEDrgb_out_0_pin3_ioTerm:PmodOLEDrgb_out_0_pin4_ioTerm:PmodOLEDrgb_out_0_pin7_ioTerm:PmodOLEDrgb_out_0_pin8_ioTerm:PmodOLEDrgb_out_0_pin9_ioTerm:Pmod_out_0_pin10_ioTerm:Pmod_out_0_pin1_ioTerm:Pmod_out_0_pin2_ioTerm:Pmod_out_0_pin3_ioTerm:Pmod_out_0_pin4_ioTerm:Pmod_out_0_pin7_ioTerm:Pmod_out_0_pin8_ioTerm:和Pmod_out_0_pin9_io 我把设计放在了Mega上 https://mega.nz/#!oplR1LCB!hg1SL ... -2JGIraXZWLBlJ29UOg 以上来自于谷歌翻译 以下为原文 I tried to set on pins oledrgb and wifi module instead of on dedicated slots so I made them external and set the xdc file but the problem is that for some reason it gives me error. [Place 30-58] IO placement is infeasible. Number of unplaced terminals (16) is greater than number of available sites (0). The following are banks with available pins: IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: BiDi RangeId: 1 Drv: 12 has only 0 sites available on device, but needs 16 sites. Term: PmodOLEDrgb_out_0_pin10_io Term: PmodOLEDrgb_out_0_pin1_io Term: PmodOLEDrgb_out_0_pin2_io Term: PmodOLEDrgb_out_0_pin3_io Term: PmodOLEDrgb_out_0_pin4_io Term: PmodOLEDrgb_out_0_pin7_io Term: PmodOLEDrgb_out_0_pin8_io Term: PmodOLEDrgb_out_0_pin9_io Term: Pmod_out_0_pin10_io Term: Pmod_out_0_pin1_io Term: Pmod_out_0_pin2_io Term: Pmod_out_0_pin3_io Term: Pmod_out_0_pin4_io Term: Pmod_out_0_pin7_io Term: Pmod_out_0_pin8_io Term: and Pmod_out_0_pin9_io I put the design on Mega https://mega.nz/#!oplR1LCB!hg1SL ... -2JGIraXZWLBlJ29UOg |
|
相关推荐
7个回答
|
|
@ tester11,
检查此AR: https://www.xilinx.com/support/answers/56354.html --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用,请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 @tester11, Check this AR: https://www.xilinx.com/support/answers/56354.html --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------View solution in original post |
|
|
|
你有太多的IO超载你的设计。
您可能在设计中定义了新的IO引脚,并忘记删除旧的分配。 不要忘记通过接受帖子作为解决方案来尽可能地关闭线程。 以上来自于谷歌翻译 以下为原文 you have overloaded your design with too many IO. you probably defined new IO pins in the design, and forgot to delete the old assignments. Don't forget to close a thread when possible by accepting a post as a solution. |
|
|
|
@ tester11,
如果您的查询已被解决,那么请您通过标记@ jmccluskas的上述帖子“接受为解决方案”来关闭此主题 --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用,请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 @tester11, If your query is addressed then Can you please close this thread by marking the above post of @jmcclusk as "Accept as Solution" --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
|
|
|
现在我面临这个错误,
[DRC UCIO-1]无约束逻辑端口:215个逻辑端口中的85个没有为用户分配特定位置约束(LOC)。 这可能导致I / O争用或与电路板电源或连接不兼容,从而影响性能,信号完整性或在极端情况下导致设备或其所连接的组件受损。 要更正此违规,请指定所有引脚位置。 除非所有逻辑端口都定义了用户指定的站点LOC约束,否则此设计将无法生成比特流。 要允许使用未指定的引脚位置创建比特流(不推荐),请使用以下命令:set_property SEVERITY {Warning} [get_drc_checks UCIO-1]。 注意:使用Vivado运行基础结构(例如,launch_runs Tcl命令)时,将此命令添加到.tcl文件,并将该文件添加为执行运行的write_bitstream步骤的预挂钩。 问题端口:GPIO_tri_o [3:0],leds_4bits_tri_io [31:0],ext_spi_clk_0,PmodOLEDrgb_out_0_pin10_io,PmodOLEDrgb_out_0_pin1_io,PmodOLEDrgb_out_0_pin2_io,PmodOLEDrgb_out_0_pin3_io,PmodOLEDrgb_out_0_pin4_io,PmodOLEDrgb_out_0_pin7_io,PmodOLEDrgb_out_0_pin8_io,PmodOLEDrgb_out_0_pin9_io,Pmod_out_0_pin10_io,Pmod_out_0_pin1_io,Pmod_out_0_pin2_io,Pmod_out_0_pin3_io ...和(第15 20个上市)。 所以我运行这个commandset_property SEVERITY {警告} [get_drc_checks UCIO-1] 但是我不知道如何将它保存在文件中并将其链接到write_bitstream。在Xilinx文档中,它说我应该在Project选项卡中选择Generate Tcl脚本,但我没有。 以上来自于谷歌翻译 以下为原文 Now I am facing this error, [DRC UCIO-1] Unconstrained Logical Port: 85 out of 215 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: GPIO_tri_o[3:0], leds_4bits_tri_io[31:0], ext_spi_clk_0, PmodOLEDrgb_out_0_pin10_io, PmodOLEDrgb_out_0_pin1_io, PmodOLEDrgb_out_0_pin2_io, PmodOLEDrgb_out_0_pin3_io, PmodOLEDrgb_out_0_pin4_io, PmodOLEDrgb_out_0_pin7_io, PmodOLEDrgb_out_0_pin8_io, PmodOLEDrgb_out_0_pin9_io, Pmod_out_0_pin10_io, Pmod_out_0_pin1_io, Pmod_out_0_pin2_io, Pmod_out_0_pin3_io... and (the first 15 of 20 listed). So I run this command set_property SEVERITY {Warning} [get_drc_checks UCIO-1] but I don't know how to save it in a file and link it to the write_bitstream.In Xilinx documentation it says that I should choose in Generate Tcl script in Project tab but I don't have it. |
|
|
|
@ tester11,
检查此AR: https://www.xilinx.com/support/answers/56354.html --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用,请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 @tester11, Check this AR: https://www.xilinx.com/support/answers/56354.html --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
|
|
|
这有帮助但是在SDK中我在xstatus.h中出现错误,即使我清理了项目
https://image.prntscr.com/image/4ciWWAr0RQOEw1bilagNGw.png 源代码文件夹上有一个X,表示文件中有错误,但没有文件上有X表示存在错误。 以上来自于谷歌翻译 以下为原文 This helped but in the SDK I get an error in xstatus.h even if I cleaned the project https://image.prntscr.com/image/4ciWWAr0RQOEw1bilagNGw.png The source code folder has an X on it that shows there is an error in a file but no file has an X on it showing that there is an error.. |
|
|
|
@ tester11,
你能否为SDK问题创建一个新的论坛帖子。 此外,由于实施问题已得到解决,请通过标记有助于“接受为解决方案”的帖子来关闭此主题 --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用,请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 @tester11, Can you please create a new forum post for SDK issue. Also since the implementation issue is resolved, please close this thread by marking the post which helped as "Accept as Solution" --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
|
|
|
只有小组成员才能发言,加入小组>>
2414 浏览 7 评论
2821 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2292 浏览 9 评论
3371 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2458 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
1069浏览 1评论
请问vc707的电源线是如何连接的,我这边可能出现了缺失元件的情况导致无法供电
577浏览 1评论
求一块XILINX开发板KC705,VC707,KC105和KCU1500
437浏览 1评论
1999浏览 0评论
722浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-12-19 18:45 , Processed in 1.412970 second(s), Total 90, Slave 74 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号