[问答]

HP 54520A示波器逻辑触发器校准失败

问答对人有帮助，内容完整，我也想知道答案 0 最近我买了一台二手HP 54520A示波器。我更新到最新固件T3.33，然后尝试进行自校准。遵循服务手册指示的所有步骤后，逻辑触发器无法校准。所有其他校准通过。除此之外，所有的自我测试都很顺利。通常我得到0xFC返回错误代码用于逻辑触发校准。但我见过0xCC，0xDC和0xEC。现在，服务手册中未记录这些错误代码。我想了解可能导致逻辑触发校准失败的原因。服务手册的故障排除部分指出它可能是通道衰减器或主板，它非常广泛。结合上述错误代码，我也查看了提供的固件。我了解到ROM和SYSTEM文件是包含WS_FILE分别为0xC30C和0xC30D文件类型的LIF文件。我想知道这些文件类型是什么（我在互联网上找不到任何资源）？我基本上在寻找标题定义。谢谢以上来自于谷歌翻译以下为原文 Recently I bought a used HP 54520A oscilloscope. I updated to latest firmware T3.33 and then attempted to do self calibration. After following all the steps as indicating by the service manual logic trigger failed to calibrate. All other calibration PASSED. In addition to this all self tests pass fine. Usually I am getting 0xFC return error code for logic trigger calibration. But I have seen 0xCC, 0xDC and 0xEC. Now, these error codes are not documented in the service manual. I would like to learn what might be the cause for logic trigger calibration failure. Troubleshooting section of the service manual states that it might be channel attenuator or main board which is pretty broad. In connection with the above error codes I also looked into the provided firmware. I learned that ROM and SYSTEM files are LIF files containing WS_FILE of 0xC30C and 0xC30D file types respectively. I am wondering what these file types are (I couldn't find any resource regarding on the Internet)? I am looking for header definition basically. Thanks 0
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答案对人有帮助，有参考价值 0 我注意到测试点TP52附近的主板“LT DLY TUNE”上的文字如下。我认为这意味着“逻辑触发延迟调谐”。我没有在电路板上看到任何允许任何调谐的元素，因此我猜测靠近测试点用于检查延迟是否在可接受的限度内。逻辑触发校准失败与此逻辑触发延迟调谐之间是否存在任何关系？是否有任何文件涵盖这些细节？我还将通道1上的衰减器/采集混合器与通道2中的衰减器进行交换。逻辑触发器校准失败，其错误代码与原始/第一个帖子（0xFC）中指示的相同。到目前为止，一切都指向主板。哪个元素可能与此校准问题有关？换句话说，这个问题是否可以修复？谢谢以上来自于谷歌翻译以下为原文 I noticed following text on the main board "LT DLY TUNE" near by test point TP52. I assume this mean "Logic Trigger Delay Tune". I didn't see any element on the board that would allow any tuning, so I am guessing that near by test point is used to check if the delay is within acceptable limits. Is there any relation in between logic trigger calibration failure and this logic trigger delay tune? Is there any document that covers these details? I also swapped attenuator/acquisition hybrid on channel 1 with the ones from channel 2. The logic trigger calibration failed with same error code as indicated in the original/first post (0xFC). So far everything points to the main board. What element might be related to this calibration issue? In other words is this problem repairable at all? Thanks

2018-11-5 10:49:00 评论举报付华一