Xilinx ISE改变信号名称影响实现

欢迎来到数字设计的乐趣！
这些过程中涉及的许多问题都是“NP难”问题（综合优化和地点和路线都是）。
结果他们用启发式“解决”了。
NP问题的启发式求解器本质上是混沌系统。
数学混沌的定义意味着对初始条件“极其”敏感的系统。
如果您为此系统提供相同的输入，它将生成相同的输出。
如果您更改输入，即使通过可能被视为不可察觉的数量，结果也可能与原始数据大不相同。
这很混乱。
所以，是的，如果你改变系统中的任何东西（RTL代码 - 是的，甚至是名称更改，约束，工具选项），即使只是一点点，你最终会得到一个不同的解决方案。
并且，是的，一个解决方案可以舒适地满足时序，并且改变后的一个可能违反时序（可能甚至很多）。
这是真的，一直是真的，可能永远是真的，并且是使用高度自动化的过程（RTL合成，自动布局和路线）来解决这些问题的不可避免的后果之一......
（抱歉）
Avrum
在原帖中查看解决方案



以下为原文

Welcome to the joys of digital design!
 
Many of the problems involved in these processes are "NP hard" problems (both synthesis optimizations and place and route are). As a result they are "solved" with heuristics. Heuristic solvers for NP problems are, by their very nature, chaotic systems.
 
The definition of mathematical chaos means a system that is "extremely" sensitive to the initial conditions. If you give this system identical inputs it will generate the same outputs. If you change the inputs, even by what may be considered an imperceptible amount, the result can be wildly different from the original. This is chaos.
 
So, yes, if you change anything in your system (RTL code - yes, even a name change, constraints, tool options) even by a tiny bit, you will end up with a different solution. And, yes, one solution may comfortably meet timing, and the one after the change may violate timing (potentially even by a lot).
 
This is true, has always been true, probably will always be true, and is one of the unavoidable consequences of using highly automated processes (RTL synthesis, automatic place and route) for these problems...
 
(Sorry)
 
Avrum
View solution in original post

欢迎来到数字设计的乐趣！
这些过程中涉及的许多问题都是“NP难”问题（综合优化和地点和路线都是）。
结果他们用启发式“解决”了。
NP问题的启发式求解器本质上是混沌系统。
数学混沌的定义意味着对初始条件“极其”敏感的系统。
如果您为此系统提供相同的输入，它将生成相同的输出。
如果您更改输入，即使通过可能被视为不可察觉的数量，结果也可能与原始数据大不相同。
这很混乱。
所以，是的，如果你改变系统中的任何东西（RTL代码 - 是的，甚至是名称更改，约束，工具选项），即使只是一点点，你最终会得到一个不同的解决方案。
并且，是的，一个解决方案可以舒适地满足时序，并且改变后的一个可能违反时序（可能甚至很多）。
这是真的，一直是真的，可能永远是真的，并且是使用高度自动化的过程（RTL合成，自动布局和路线）来解决这些问题的不可避免的后果之一......
（抱歉）
Avrum



以下为原文

Welcome to the joys of digital design!
 
Many of the problems involved in these processes are "NP hard" problems (both synthesis optimizations and place and route are). As a result they are "solved" with heuristics. Heuristic solvers for NP problems are, by their very nature, chaotic systems.
 
The definition of mathematical chaos means a system that is "extremely" sensitive to the initial conditions. If you give this system identical inputs it will generate the same outputs. If you change the inputs, even by what may be considered an imperceptible amount, the result can be wildly different from the original. This is chaos.
 
So, yes, if you change anything in your system (RTL code - yes, even a name change, constraints, tool options) even by a tiny bit, you will end up with a different solution. And, yes, one solution may comfortably meet timing, and the one after the change may violate timing (potentially even by a lot).
 
This is true, has always been true, probably will always be true, and is one of the unavoidable consequences of using highly automated processes (RTL synthesis, automatic place and route) for these problems...
 
(Sorry)
 
Avrum

与您的项目一样，您最好的选择是使用Smart Xplorer以及一系列起始放置成本表种子。
如上所述，这些工具从一个看似随机的位置开始，然后使用一些可能涉及一系列放置交换的专有算法进行“最佳”放置。
在任何情况下，“最佳”放置实际上只是路由长度中的局部最小值，因为已经指出找到路由长度的绝对最小值是不可解决的。
这就像旅行推销员的问题，有成千上万的地方可以访问，而且多个推销员需要分享道路而不会产生太多的流量......
即使您找到了可行的种子，每次进行一次小改动时，您仍需要回到Smart Xplorer。
但是我发现锁定设计的一部分可能会有所帮助。
通常，当您找到可行的解决方案时，它有助于锁定非结构元素（如BRAM，时钟缓冲区和DSP）的位置。
这通常有助于工具在下一次融合到类似的解决方案上。
您也可以使用引导式放置，但这有一些缺点。
主要缺点是该指南基于已经包装好的切片。
这意味着即使设计中的微小变化也可能最终导致切片名称的大量差​​异，从而导致非导向单元格。
-  Gabor



以下为原文

Your best bet with projects like yours is to use Smart Xplorer with a range of starting placement cost table seeds.  As noted, the tools start with a seemingly random placement and then work to a "best" placement using some proprietary algorithm that probably involves a series of placement swaps.  In any case, the "best" placement is really only a local minimum in the routing length, because as already pointed out finding the absolute minimum in routing length would not be solvable.  It's something like the traveling salesman problem with thousands of places to visit and multiple salesmen that need to share the road without creating too much traffic...
 
Even after you find a seed that works, you still need to go back to Smart Xplorer each time you make even a small change.  However I have found that locking down a portion of the design can be helpful.  Typically when you find a working solution, it helps to lock down the position of non-fabric elements like BRAM, clock buffers, and DSP.  This often helps to tools to converge on a similar solution the next time around.  You can also use guided placement, however that has some drawbacks.  The main drawback is that the guide is based on already packed slices.  That means that even a small change in the design can end up with a large number of differences in slice names, and hence non-guided cells.
-- Gabor

嗨Avrum和Gabor，
非常感谢您的快速回答，并对我延迟回复感到抱歉。
我相信你们所说的一切都是正确的，但它仍然让我感到有些不安！
我可以理解，对RTL行为，约束或工具设置的更改会导致不同的实现，从而导致时间，但信号名称*应该*只被视为标签，理想情况下不会更改结果。
实际上，我验证了（使用ngc2edif和diff）来自XST的合成网表（对于具有不同命名信号的两个设计）是相同的，以名称本身为模。
无论如何，我现在明白了在我的示例设计中导致时序结果的疯狂变化的原因。
因为我只是实现了设计的一部分（只是为了感觉一些子模块的时序收敛）我没有找到任何引脚分配，因此工具可以自由浮动顶层IO引脚
。
实际上，（任意）分配LOC约束在更改信号名称时会产生更多的一致结果，尽管由于您描述的原因不同，但变化大大减少了。
这让我有信心，一个舒适地满足时间的设计，应该继续这样做，例如当计数器的名称改变时。
我不认为我曾经尝试使用Smart Xplorer，但我记得我经常需要使用Multi-pass place＆amp;
过去的路线。
我的印象是，MPPR更少被物理综合和时间驱动的地图所取代，这往往比改变砂种更好。
我也尝试过导游P＆amp; R，并取得了不同程度的成功。
如果我现在有计时问题，我倾向于首先尝试在RTL级别修复问题，然后使用高级约束（例如假路径），如果可行的话，而不是在可能的情况下改变工具设置。
再次感谢你的帮助。
格伦。



以下为原文

Hi Avrum and Gabor,
 
Many thanks for your prompt answers, and sorry for my delay in replying. I am sure everything you both say is correct, but it still leaves me with a bit of queasy feeling! I can understand that changes to the RTL behaviour, constraints, or tool settings would result in a different implemention and hence the timing, but signal names *ought* to just be treated as labels, and ideally not change the result. In fact, I verified (using ngc2edif, and diff) that the syntheisised netlists from XST (for two designs with differently named signals) were identical, modulo the names themselves.
 
Anyway, I understand a bit better now what was causing the wild variation in timing results in my example designs. As I was only implementing part of a design (just to get a feel for the timing closure of a few submodules) I had not loc'ed down any pin assignments, and so the tools were free to freely float the top-level IO pins. Indeed, (arbitrarliy) assigning LOC constraints gave much more constistent results when changing signal names, although not identical for reasons you both describe, the variation was much reduced. This gives me some confidence that a design which comfortably meets timing, should continue to do so, for example when just the name of a counter is changed.
 
I don't think I have ever tried using Smart Xplorer but I remember I often needed to use Multi-pass place & route in the past. My impression was that MPPR had more of less been superseded by things like physical synthesis and timing-driven map, which tend to give much better results than changing the placer seed. i have also tried guided P&R with variable success. If I have timing problems these days I tend to try to fix things at the RTL level first, and then with advanced constraints, such as false paths, if appropriate, rather than varying tool settings if I can.
 
Thanks again for your help.
 
Glenn.

MPPR被Smart Xplorer取代。
有更多的模式只使用成本表种子，但在该模式下，它基本上是多遍Map / Place＆amp; Route。
这是必要的，因为在较新版本的ISE中映射期间会进行放置。
在ISE中，您可以手动更改Map和Place＆amp; Route的成本表种子，但它实际上只影响Map。
如果两个种子不匹配，您会收到警告。
另一个Smart Xplorer模式是尝试不同的固定设置（除了成本表种子）以查看它们中的任何一个是否适合您的项目。
我很少使用这种模式，因为我已经使用ISE很长时间了，并且发现了对于给定类型的设计最适合我的设置。
Smart Xplorer在固定套装中更改的所有内容都可以在Map和Place＆amp; Route的属性中单独调整。
-  Gabor



以下为原文

MPPR is replaced by Smart Xplorer.  There are more modes that just playing with cost table seeds, however in that mode it is essentially multi-pass Map/Place&Route.  That is necessary because placement occurs during mapping in the newer versions of ISE.  In ISE you can manually change the cost table seed for both Map and Place&Route, but it really only affects Map.  You get a warning if the two seeds don't match.
 
Another Smart Xplorer mode is to try different sets of canned settings (other than cost table seeds) to see if any of them works better for your project.  I rarely use this mode, since I've been using ISE for a long time and have discovered the settings that work best for me for a given type of design.  Everything that Smart Xplorer changes in the canned sets can be tweaked individually in the properties for Map and Place&Route.
-- Gabor

谢谢Gabor，
如果我将来遇到计时困难，我可能会再次尝试SmartXplorer。
和你一样，我倾向于知道哪种工具适用于我的设计，并且我使用合成属性在本地覆盖这些信号，这些信号偏离了默认设置。
干杯，
格伦。



以下为原文

Thanks Gabor,
 
I may try SmartXplorer again if I run into timing difficulties in the future. Like you, I tend to know which tool work for my designs, and I override these locally with synthesis attributes for signals which diverge from the default settings.
 
Cheers,
Glenn.