我怎么告诉Vivado我的信号是差分的？

嗨，
我有这个设计：
模块顶部
（A_N，A_P，B_N，B_P）;
输入A_N;
输入A_P;
输出B_N;
输出B_P;
分配B_N = A_N;
分配B_P = A_P;
系统
system_i（
.CLK_P（A_P），
.CLK_N（A_N）
）;
endmodule
我使用LVDS标准将A_N，A_P，B_N和B_P连接到XDC文件中的物理引脚。
在Vivado中，综合是成功的，但实现失败并出现以下错误：
[Drc 23-20]规则违规（IOSTDTYPE-1）IOStandard类型 -  I / O端口B_N是单端但具有LVDS的IOS标准，只能支持差分
[Drc 23-20]规则违规（IOSTDTYPE-1）IOStandard类型 -  I / O端口B_P是单端但具有LVDS的IOS标准，只能支持差分
如果我没有将A_N和A_P连接到“system”模块（这是micrlaze），我也得到了与A_N和A_P相同的错误。
不知何故，Vivado不知道B_N和B_P是差分对。
我该如何判断它们是什么？
也可能是合成正在消除这两个信号，因为它们没有被“使用”。
在那种情况下，我该如何避免呢？
基本上，我想要做的就是将A_N和A_P连接到两组不同的物理引脚，但由于我不允许这样做，所以我基本上复制了A_N和A_P。
任何帮助深表感谢。
如果您有任何建议或更好的方法来实现我的目标，请告诉我。
谢谢，



以下为原文

Hi,

I have this design:

module top  (
A_N,
A_P,
B_N,
B_P
);  input A_N;
input A_P;

output B_N;
output B_P;

assign B_N = A_N;
assign B_P = A_P;
    system    system_i (      .CLK_P ( A_P ),      .CLK_N ( A_N )    );endmodule
I have hooked up A_N, A_P, B_N, and B_P to physical pins in the XDC file using the LVDS standard. In Vivado, synthesis is successul but implementation fails with these errors:

[Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port B_N is Single-Ended but has an IOStandard of LVDS which can only support Differential
[Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port B_P is Single-Ended but has an IOStandard of LVDS which can only support Differential

If I don't hook up A_N and A_P to the "system" module (this is microblaze), I get the same erros for A_N and A_P, also. Somehow, Vivado doesn't know that B_N and B_P are differential pairs. How can I tell it that they are?

It could also be that synthesis is removing these two signals because they're not "used". In that case how can I avoid that?

Essentially, all I want to do is connect A_N and A_P to two different sets of physical pins, but since I'm not allowed to do that, I'm basically duplicating A_N and A_P.

Any help is much appreciated. If you have any advice or a better way to accomplish my goal, pleae let me know.

Thanks,