路由占用太多时间

嗨，您使用的是哪种操作系统？请更改实施策略并运行。
谢谢，维杰-----------------------------------------------
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以下为原文

Hi,
Which OS are you using?
Please change the implementation strategies and run.Thanks,Vijay
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我正在使用Windows 7.您推荐的实施策略中是否有特定的内容？



以下为原文

I am using windows 7. is there something specific in implementation stratgies you recomend?

嗨，尝试Flow_RuntimeOptimized有关更多信息，请参阅http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug904-vivado-implementation.pdf的第137页。
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以下为原文

Hi,
Try Flow_RuntimeOptimized
Refer to page 137 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug904-vivado-implementation.pdf for more informationThanks,Vijay
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从日志来看，由于节点重叠很多，它看起来似乎是一个拥挤的设计。
你可以运行一些策略：
＃1
Place_design -directive探索
Route_design -directive探索
＃2
place_design -directive ExtraNetDelay_high
phys_opt_design -directive AggressiveFanoutOpt
route_design -directive MoreGlobalIterations
＃3
place_design -directive ExtraNetDelay_high
route_design -directive MoreGlobalIterations
＃4
place_design -directive ExtraNetDelay_high
route_design -directive HigherDelayCost
试试这些。
希望这可以帮助。
问候
Sikta



以下为原文

From the log, It definitely seems a congested design as there are lot of node overlaps.
 
 
Can you run some strategies:
 
#1
Place_design –directive Explore
Route_design –directive Explore
 
#2
place_design -directive ExtraNetDelay_high
phys_opt_design -directive AggressiveFanoutOpt
route_design -directive MoreGlobalIterations
 
#3
place_design -directive ExtraNetDelay_high
route_design -directive MoreGlobalIterations
 
#4
place_design -directive ExtraNetDelay_high
route_design -directive HigherDelayCost
 
Try with these. Hope this helps.
 
Regards
Sikta

嗨，
我假设您正在使用sysem版许可证，否则这可能是问题所在。
您还可以列出MIG和TRIMAC以及您的自定义逻辑模块的模块级利用率
你自己的逻辑包含什么？
如果你评论自己的逻辑需要多长时间？
如果相关问题适用于您，请检查相关讨论。请按照建议进行操作
http://forums.xilinx.com/t5/Implementation/Vivado-implementation-taking-too-long-using-RPMs/td-p/485428
http://forums.xilinx.com/t5/Implementation/Place-amp-Route-takes-too-long/td-p/481410
http://forums.xilinx.com/t5/Embedded-Processor-System-Design/How-long-to-implement-a-vivado-project/td-p/449466
问候，
Vanitha
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以下为原文

Hi,
 
I assume you are using sysem edition license, else this can be the issue.
 
Also can you list out module level utilization for MIG and TRIMAC and your custom logic module
What does your own logic contains?
How much time did it take if you comment out your own logic?
 
Please check relavant discussions if in case they apply to you..follow the suggestions
http://forums.xilinx.com/t5/Implementation/Vivado-implementation-taking-too-long-using-RPMs/td-p/485428
 
http://forums.xilinx.com/t5/Implementation/Place-amp-Route-takes-too-long/td-p/481410
 
http://forums.xilinx.com/t5/Embedded-Processor-System-Design/How-long-to-implement-a-vivado-project/td-p/449466
 
 
Regards,
Vanitha
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