PlanAhead实施出错

你想用哪种IP？
如果它与设备无关，我建议尝试使用其他设备。
这将确认问题是否与IP或设备部件有关。
问候
Sikta



以下为原文

Which IP are you trying to use? If it has nothing to do with a device, I would suggest trying with a different device.
 
This will confirm if the problem has to do with IP or the device part.
 
Regards
Sikta

嗨，
错误表示设计中的IO端口数超过了设备中的IOB数。
检查设计中的顶级端口，看看是否可以减少它们。
否则瞄准更大的设备。
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
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以下为原文

Hi,
 
The error says that the number of IO ports in the design exceeds the number of IOB's in the device.
 
Check the top level ports in the design and see if you can reduce them. Else target a bigger device.
 
Thanks,
Deepika.
Thanks,
Deepika.
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你好
资源表清楚地表明您的设备使用了136％的IO（过度使用）设备中存在的IO数量。
你必须要处理这个问题，看起来你正在将逻辑端口作为顶级引脚。
问候，萨蒂什-----------------------------------------------
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以下为原文

Hi
 
The resource table clearly indicates that your desing is using 136% of IO's(overutilizing) the number of IO's present in the device.
 
You have to take care of this,looks like you are making logical ports also as top level pins.
Regards,

Satish

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我只是写了一个非常简单的ip核心，它只显示一个充满红色像素的静态图片。
主要问题是，任何选项是否可以优化合成和实现，绝对不是缺乏芯片资源。
我重写了逻辑电路，问题就没了。



以下为原文

I just write a very easy ip core , it just displays a static picture ,full of red pixels. the main problem is that whether  any  option can optimize the sythesis  and implementation, it is absolutely not  the lack of the chip resource.
 
I rewrite the logic circuit, and the problem gone.

嗨，
错误表示设计中的顶级端口数超过了设备中的可用封装引脚。
该工具可以优化逻辑，但不能优化/删除顶级端口。
您需要像更改顶级端口的数量一样对设计进行更改。
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
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张贴。
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以下为原文

Hi,
 
The error says that the number of top level ports in your design exceeds the available package pins in the device.
 
The tool can optimize the logic but it cannot optimize/remove the top level ports. You need to make changes to the design as you did to reduce the number of top level ports.
 
Thanks,
Deepika.
Thanks,
Deepika.
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嗨，转到实施板。
谢谢，维杰-----------------------------------------------
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以下为原文

Hi,
Moving to implementation board.Thanks,Vijay
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