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你好,
关于本主题中提到的微控制器中的异常,我有几个问题。 我试图通过用0x0000替换十六进制的一部分来导致非法指令异常(IVOR6)。根据PowerISA v2.06B''完全由binaly 0组成的指令是非法的,并且在该体系结构的所有未来版本中都被保证是非法的''。这个问题也不例外。据我所知,这个例外是不可屏蔽的,因此在假设满足要求时应始终采用。我也尝试将程序计数器写入由全0组成的内存区域,并且没有异常。这种行为是否正确?如何导致此异常? 如何将十六进制代码转换为微控制器执行的指令,十六进制代码似乎与e200z4核心文档中提供的操作码不对应? 当exacly是浮点不可用(IVOR7)和SPE不可用(IVOR32)异常?如果MSR [FP] = 0且MSR [SPE] = 0并且通过执行efsdiv操作执行浮点除法,则不会发生异常。这种行为是否正确?最好的问候 以上来自于谷歌翻译 以下为原文 Hello, I have a few questions regarding exceptions in microcontroller mentioned in the topic. I'm trying to cause Illegal instruction exception (IVOR6) by substituting part of hex with 0x0000. According to PowerISA v2.06B ''an instruction consisting entirely of binaly 0s is illegal, and is quaranteed to be illegal in all future versions of this architecture''. The problem is no exception is taken. From what i know this exception is not maskable so it always should be taken assuming requirements are met. I also tried writing program counter to memory region consisting of all 0s and no exception is taken. Is this behaviour correct and how can I cause this exception? How can i translate hex code to instructions performed by microcontroller, hex code doesn't seem to correspond to opcodes presented in e200z4 core documentation? When exacly are Floating-point unavailable (IVOR7) and SPE Unavailable (IVOR32) exceptions taken? If MSR[FP] = 0 and MSR[SPE] = 0 and division of floating-point is performed by execution of efsdiv operation, no exception is taken. Is this behaviour correct?Best regards |
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你好Dariusz,
SPC56EL60L5CBF具有良好的信号处理引擎。 1)关于非法例外(IVOR6),是的,''指令完全由二进制0组成是非法的'' 它应该是非法的,应该处理IVOR6。无论如何,我正在与专家交叉核对为什么不处理IVOR6。 2)关于HexCode,您是否检查了PowerISA V2.06B中的附录A. 最后一位efsdiv应该是2C9 就我而言,它在我的HEX代码和附录A之间匹配 (使用SPC5Studio进行测试) 3) *)对于e200,硬件不支持浮点单元,未实现浮点单元 将尝试执行Power ISA嵌入式操作异常 FP设置时的类别浮点指令(不是IVOR7) *)MSR [SPE]定义为SPE / EFPU可用位。 如果MSR [SPE] = 0并且通过执行efsdiv操作执行浮点除法,则不应发生异常。行为是正确的;-) ''如果MSR [SPE]被清除并执行SPE指令,则采用SPE不可用异常 尝试标量浮点指令(efsxxx)或brinc,或执行EFPU evfsxx 尝试指示。'' 最好的祝福 二万 以上来自于谷歌翻译 以下为原文 Hello Dariusz , SPC56EL60L5CBF has well a Signal Processing Engine. 1) About Illegal Exception (IVOR6), Yes , ''An instruction is consisting entirely of binary 0s is illegal'' it should be illegal and IVOR6 should be handled. Anyway, I am cross-checking with experts why IVOR6 is not handled. 2) about HexCode , Did you check Appendix A in PowerISA V2.06B the last bits efsdiv should be 2C9 in my case , it matches between my HEX code and the appendix A (Test done with SPC5Studio) 3) *)For the e200, the floating point unit is not supported in hardware, and an unimplemented operation exception will be generated for attempted execution of Power ISA embedded category floating point instructions when FP is set (not IVOR7) *)MSR[SPE] is defined as the SPE/EFPU available bit. if MSR[SPE] = 0 and division of floating-point is performed by execution of efsdiv operation, the exception should not be happened. The behavior is correct ;-) ''The SPE unavailable exception is taken if MSR[SPE] is cleared and execution of an SPE instruction other than the scalar floating-point instructions (efsxxx) or brinc is attempted, or execution of a EFPU evfsxx instruction is attempted.'' Best regards Erwan |
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你好,
1)非常感谢您发现的信息。 2)我正在使用Trace32和Lauterbach调试器以防万一。让我们考虑lwz(加载字和零)操作。在软件中,我发现了3次此操作: C007 se_lwz r0,0x0(r7) 操作码目标源 1100 00 | 00 000 | 0 0111 0x30 0x0 0x7 - 0x30是lfs(加载浮点单) 50E836E0 e_lwz r7,0x36E0(r8) 操作码目标源参数 0101 00 | 00 111 | 0 1000 | 0011 0110 1110 0000 0x14 0x7 0x8 0x36E0 - 0x14是rlwimi(旋转左词immed然后掩码插入) 514836E0 e_lwz r10,0x36E0(r8) 0101 00 | 01 010 | 0 1000 | 0011 0110 1110 0000 0x14 0xA 0x8 0x36E0 帮助我理解这一点。根据e200z4核心和Power ISA文档,lwz操作的操作码应为100000(0x32)。我错过了什么,或者我只是简单的愚蠢:] 非常感谢您的帮助 最好的祝福 以上来自于谷歌翻译 以下为原文 Hello, 1) Would be grateful for information what you found out. 2) I'm using Trace32 and Lauterbach debugger in case this matters. Let's consider lwz (Load Word & Zero) operation. In software i found 3 occurences of this operation: C007 se_lwz r0, 0x0(r7) opcode target source 1100 00|00 000|0 0111 0x30 0x0 0x7 - 0x30 is lfs (load floating-point single) 50E836E0 e_lwz r7, 0x36E0(r8) opcode target source argument 0101 00|00 111|0 1000| 0011 0110 1110 0000 0x14 0x7 0x8 0x36E0 - 0x14 is rlwimi (rotate left word immed then mask insert) 514836E0 e_lwz r10, 0x36E0(r8) 0101 00|01 010|0 1000| 0011 0110 1110 0000 0x14 0xA 0x8 0x36E0 Help me understand this. According to e200z4 core and Power ISA documentation opcode for lwz operation should be 100000 (0x32). Am i missing something or am i just plain stupid :] Thank you very much for your help Best regards |
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大流士你好,
1)我们正在继续调查 2)它匹配得很好,你的操作码计算不好。 (见下文) Cf附录A. se_lwz se_lwz r0,0x0(r7)==> SD4 ---- VLE se_lwz加载Word和Zero Short Form 1100 00 | 00 000 | 0 0111 0x30 0x0 0x7 - 0x30是lfs(加载浮点单) 1100 0000 | 0000 0111 e_lwz r7,0x36E0(r8)==> D VLE e_lwz加载Word和Zero e_lwz r10,0x36E0(r8)==> D VLE e_lwz加载Word和Zero 最好的祝福 二万 以上来自于谷歌翻译 以下为原文 Hello Darius , 1) we are continuing to investigate 2) it matches well , your opcode calculation is just not good. (Cf Below) Cf APPENDIX A se_lwz se_lwz r0, 0x0(r7) ==> SD4 ---- VLE se_lwz Load Word and Zero Short Form 1100 00|00 000|0 0111 0x30 0x0 0x7 - 0x30 is lfs (load floating-point single) 1100 0000 | 0000 0111 e_lwz r7, 0x36E0(r8) ==> D VLE e_lwz Load Word and Zero e_lwz r10, 0x36E0(r8) ==> D VLE e_lwz Load Word and Zero Best Regards Erwan |
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你好,
关于调查为何没有调用非法例外的任何结果? 以上来自于谷歌翻译 以下为原文 Hello, Any results on the investigation why Illegal Exception is not called? |
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你好Dariusz,
当SE_ILLEGAL像NOP一样考虑时,你能给你的MSR配置吗? se_illegal用于请求非法指令异常。生成程序中断。内容 MSR的数据被复制到SRR1中,se_illegal指令的地址被放入SRR0。 MSR [WE,EE,PR,IS,DS,FP,FE0,FE1]被清除。 最好的祝福 二万 以上来自于谷歌翻译 以下为原文 Hello Dariusz , Could you give your MSR Configuration when SE_ILLEGAL is taking acccount like a NOP ? se_illegal is used to request an illegal instruction exception. A program interrupt is generated. The contents of the MSR are copied into SRR1 and the address of the se_illegal instruction is placed into SRR0. MSR[WE,EE,PR,IS,DS,FP,FE0,FE1] are cleared. Best Regards Erwan |
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