MAP使用行为代码中的专用硬件只得到LUT

嗨，
您可以在HDL中使用USE_DSP48属性来强制在DSP上实现逻辑。
有关约束使用的详细信息，请参阅http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/xst_v6s6.pdf的第443页。
谢谢，
迪皮卡。
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以下为原文

Hi,
 
You can use USE_DSP48 attribute in HDL to force implementation of logic on to DSP.
 
Refer to page-443 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/xst_v6s6.pdf for details on constraint usage.
 
Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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嗨，
您可以在HDL中使用USE_DSP48属性来强制在DSP上实现逻辑。
有关约束使用的详细信息，请参阅http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/xst_v6s6.pdf的第443页。
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）



以下为原文

Hi,
 
You can use USE_DSP48 attribute in HDL to force implementation of logic on to DSP.
 
Refer to page-443 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/xst_v6s6.pdf for details on constraint usage.
 
Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

非常感谢，它的确有效。
我在实体声明中添加了： 
attribute use_dsp48：string; 
adder的属性use_dsp48：entity是“yes”;
我唯一不明白的是为什么DSP Slice实现比LUT实现慢？
我认为专用硬件总是比一般逻辑更快。



以下为原文

Thank you very much, it works. I added within the entity declaration:
    attribute use_dsp48 : string;    attribute use_dsp48 of Adder : entity is "yes"; 
The only thing I don't understand is why is the DSP slice implementation slower than the LUT implementation? I thought dedicated hardware would be always faster than general logics.

vaclav写道：
我唯一不明白的是为什么DSP Slice实现比LUT实现慢？
我认为专用硬件总是比一般逻辑更快。
也许是加法器的路由是缓慢的部分。
确保注册了加法器输入。
----------------------------是的，我这样做是为了谋生。



以下为原文

vaclav wrote:
 
The only thing I don't understand is why is the DSP slice implementation slower than the LUT implementation? I thought dedicated hardware would be always faster than general logics.

Perhaps it's the routing into the adder that's the slow part. Make sure the adder input is registed.
----------------------------Yes, I do this for a living.

我注册了输出而不是输入。
我想要一个单循环加法器，所以我不能同时拥有这两个加法器。



以下为原文

I made the output registered and not the input. I want a single cycle adder, so I can't have both.

vaclav写道：
我注册了输出而不是输入。
我想要一个单循环加法器，所以我不能同时拥有这两个加法器。
记住时序分析器如何计算周期。
它是从一个寄存器的Q输出，通过任何逻辑，到下一个寄存器的D输入。
如果在您的输入点击加法器的输入之前有“东西”，则“填充”会增加道具延迟。
您的选择包括流水线操作，接受降低的操作频率以及接受延迟。
----------------------------是的，我这样做是为了谋生。



以下为原文

vaclav wrote:
I made the output registered and not the input. I want a single cycle adder, so I can't have both.

remember how the timing analyzer calculates the period. It's from one register's Q output, through whatever logic, to the next register's D input. If there is "stuff" before your inputs hit the adder's inputs, that "stuff" adds to the prop delay.
 
Your choices include pipelining, accepting the reduced operating frequency, and accepting the latency.
----------------------------Yes, I do this for a living.