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嗨,
我正在开发一种设计,其中WNS报告为85 ns,源和目标寄存器之间有153个组合级别。 它处于同一时钟域。 是否有一个设置,我可以约束vivado说我可以限制regiaters之间的组合逻辑级别的数量。 谢谢 阿尼尔 以上来自于谷歌翻译 以下为原文 Hi , I am working on a design in which it has reported the WNS as 85 ns and there is 153 combo levels in between source and destination register. It is in the same clock domain. Is there a setting where I can constrain vivado to say that I can limit the number of combo logic levels between the regiaters. Thanks Anil |
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4个回答
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设计中逻辑级别的数量是您的设计综合的结果,因此它是您生成的设计实现的固有属性。
Vivado只是尽可能地实现您的RTL,并告诉您它是否能够根据您生成的约束来满足时序要求。 如果您希望逻辑电平的数量更少,则必须更改您的设计,即RTL以简化逻辑,以便产生更少的逻辑电平。 这可以通过将逻辑分解为更小的部分并在其间添加管道寄存器来实现。 如果您发布生成此-85ns路径的RTL,我们可以提供一些建议。 - 如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。 以上来自于谷歌翻译 以下为原文 The number of logic level in the design is a result of synthesis of your design so it is an inherent property of the design implementation which is produced by you. Vivado just implements your RTL as best as it can and tells you if it can meet timing based on the constraints you generate. If you want the number of logic levels to be fewer, you have to change your design, ie RTL to simplify the logic so that it would produce fewer logic levels. This can be accomplished by breaking down your logic into smaller sections and adding pipeline registers in between. If you post the RTL which is producing this -85ns path, we can give some suggestions. - Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. |
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嗨Anil,
Vivado Synthesis存在一个已知问题,在2013年为包含由LUT分隔的进位链的FSM添加了太多级别的逻辑。 您使用的是哪个版本的工具? 你在说什么样的逻辑? 比较? 问候 Sikta 以上来自于谷歌翻译 以下为原文 Hi Anil, There was a known issue with Vivado Synthesis adding too many levels of logic for FSM containing carry chains separated by LUTs in 2013.2. Which version of tools are you using? What kind of logic are you wrting? Comparators? Regards Sikta |
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通过检查网表和代码来检查综合结果。
如果没有预料到,那可能是一个综合问题。 否则,尝试修改rtl代码。 问候,brucey ----------------------------------------------- - - - - - - - - - - - - - - - - - - - - - - - -请注意- 如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。感谢Kudos .-------------------- -------------------------------------------------- ------------------------ 以上来自于谷歌翻译 以下为原文 Check the synthesis result by examining the netlist and code. If it's not expected, it may be one synthesis issue. Otherwise, try to modify rtl code. Regards, brucey ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- |
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