在National仪器上对CLIP进行了更改得到一个错误

大家好，
我在National仪器上对CLIP（NI6587连接器Serdes）进行了更改，我得到一个错误编译如下：
labview FPGA：La compilationaéchouéàinssed'une erreur Xilinx。
详细信息：错误：位置：906  - 由于位置限制导致违反时钟区域规则，因此无法放置和路由由IO时钟网络驱动的组件。
IO时钟网被BUFIO驱动锁定到站点“BUFIO_X0Y11”由于这个位置约束，只能驱动时钟区域“CLOCKREGION_X0Y2”。
驱动的以下组件已锁定到这些时钟区域之外的站点：Puma20Window / theCLIPs / IO_Module_CLIP0 / Ni6587CoreSerdesx / GenerationEnginex / Dat aSer / SerialGen [0] .MasterOserdes（锁定站点：OLOGIC_X0Y133 CLOCKREGION_X0Y3）Puma20Window / theCLIPs / IO_Module_CLIP0 / Ni6587CoreSerdesx /
GenerationEnginex / Dat aSer / SerialGen [1] .SlaveOserdes（锁定站点：OLOGIC_X0Y144 CLOCKREGION_X0Y3）Puma20Window / theCLIPs / IO_Module_CLIP0 / Ni6587CoreSerdesx / GenerationEnginex / Dat aSer / SerialGen [4] .MasterOserdes（锁定站点：OLOGIC_X0Y115 CLOCKREGION_X0Y2）Puma20Window / theCLIPs / IO_Module_CLIP0 /
Ni6587CoreSerdesx / GenerationEnginex / DAT ASER / SerialGen [9] .SlaveOserdes（锁定位置：OLOGIC_X0Y104 CLOCKREGION_X0Y2）Puma20Window / theCLIPs / IO_Module_CLIP0 / Ni6587CoreSerdesx / GenerationEnginex / DAT ASER / SerialGen [8] .MasterOserdes（锁定位置：OLOGIC_X0Y113 CLOCKREGION_X0Y2）Puma20Window / theCLIPs /
IO_Module_CLIP0 / Ni6587CoreSerdesx / GenerationEnginex / Dat aSer / SerialGen [6] .SlaveOserdes（锁定站点：OLOGIC
_X0Y96 CLOCKREGION_X0Y2）Puma20Window / theCLIPs / IO_Module_CLIP0 / Ni6587CoreSerdesx / GenerationEnginex / DAT ASER / SerialGen [1] .MasterOserdes（锁定位置：OLOGIC_X0Y145 CLOCKREGION_X0Y3）Puma20Window / theCLIPs / IO_Module_CLIP0 / Ni6587CoreSerdesx / GenerationEnginex / DAT ASER / SerialGen [3] .SlaveOserdes（锁定
网站：OLOGIC_X0Y158 CLOCKREGION_X0Y3）Puma20Window / theCLIPs / IO_Module_CLIP0 / Ni6587CoreSerdesx / GenerationEnginex / DAT ASER / SerialGen [5] .MasterOserdes（锁定部位：OLOGIC_X0Y107 CLOCKREGION_X0Y2）Puma20Window / theCLIPs / IO_Module_CLIP0 / Ni6587CoreSerdesx / GenerationEnginex / DAT ASER / SerialGen [0] .SlaveOserdes
（锁定位置：OLOGIC_X0Y132 CLOCKREGION_X0Y3）Puma20Window / theCLIPs / IO_Module_CLIP0 / Ni6587CoreSerdesx / GenerationEnginex / DAT ASER / SerialGen [9] .MasterOserdes（锁定位置：OLOGIC_X0Y105 CLOCKREGION_X0Y2）Puma20Window / theCLIPs / IO_Module_CLIP0 / Ni6587CoreSerdesx / GenerationEnginex / DAT INFO：TclTask​​sC：1850  -
流程运行：地图完成。
ASER / SerialGen [8] .SlaveOserdes（锁定位置：OLOGIC_X0Y112 CLOCKREGION_X0Y2）Puma20Window / theCLIPs / IO_Module_CLIP0 / Ni6587CoreSerdesx / GenerationEnginex / DAT ASER / SerialGen [2] .MasterOserdes（锁定位置：OLOGIC_X0Y155 CLOCKREGION_X0Y3）Puma20Window / theCLIPs / IO_Module_CLIP0 / Ni6587CoreSerdesx / GenerationEnginex
/ DAT ASER / SerialGen [5] .SlaveOserdes（锁定位置：OLOGIC_X0Y106 CLOCKREGION_X0Y2）Puma20Window / theCLIPs / IO_Module_CLIP0 / Ni6587CoreSerdesx / GenerationEnginex / DAT ASER / SerialGen [6] .MasterOserdes（锁定位置：OLOGIC_X0Y97 CLOCKREGION_X0Y2）Puma20Window / theCLIPs / IO_Module_CLIP0 / Ni6587CoreSerdesx
/ GenerationEnginex / Dat aSer / SerialGen [2] .SlaveOserdes（锁定站点：OLOGIC_X0Y154 CLOCKREGION_X0Y3）Puma20Window / theCLIPs / IO_Module_CLIP0 / Ni6587CoreSerdesx / GenerationEnginex / Dat aSer / SerialGen [3] .MasterOserdes（锁定站点：OLOGIC_X0Y159 CLOCKREGION_X0Y3）请评估位置约束
BUFIO和驱动的组件都确保它们遵循a的时钟区域规则
体系结构的设计。
有关时钟区域规则的更多信息，请参阅体系结构用户指南。
要使用部分路由设计调试您的设计，请允许mapper / placer完成执行（通过将环境变量XIL_PAR_DEBUG_IOCLKPLACER设置为1）。
阶段7.2初始时钟和IO放置（校验和：a3d3c539）实时：1分35秒
Placer完成的实际总时间：1分35秒完成Placer完成的总CPU时间：59秒ERROR：Pack：1654  - 时序驱动的放置阶段遇到错误。
映射已完成。
有关详细信息，请参阅MAP报告文件“Puma20Top_map.mrp”。
包装阶段遇到的问题。
设计摘要--------------错误数：2警告数：442
处理“地图”失败
非常感谢您的帮助。
问候，
丹尼斯。
NI6587ConnectorSerdesOLED.zip 31 KB



以下为原文

Hello everybody,

I make a change in the CLIP (NI6587 Connector Serdes) from National instrument and I get an error compilation following :

LabVIEW FPGA:  La compilation a échoué à cause d'une erreur Xilinx.
Details: ERROR:Place:906 - Components driven by IO clock net    can't    be placed and routed because location constraints are causing the clock    region rules to be violated. IO Clock net    is    being driven by BUFIO    locked to site "BUFIO_X0Y11" Because of this    location contraint,    can    only drive clock region "CLOCKREGION_X0Y2". The following components driven    by have    been locked to sites outside of these clock regions:    Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat    aSer/SerialGen[0].MasterOserdes (Locked Site: OLOGIC_X0Y133 CLOCKREGION_X0Y3)    Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat    aSer/SerialGen[1].SlaveOserdes (Locked Site: OLOGIC_X0Y144 CLOCKREGION_X0Y3)    Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat    aSer/SerialGen[4].MasterOserdes (Locked Site: OLOGIC_X0Y115 CLOCKREGION_X0Y2)    Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat    aSer/SerialGen[9].SlaveOserdes (Locked Site: OLOGIC_X0Y104 CLOCKREGION_X0Y2)    Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat    aSer/SerialGen[8].MasterOserdes (Locked Site: OLOGIC_X0Y113 CLOCKREGION_X0Y2)    Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat    aSer/SerialGen[6].SlaveOserdes (Locked Site: OLOGIC_X0Y96 CLOCKREGION_X0Y2)    Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat    aSer/SerialGen[1].MasterOserdes (Locked Site: OLOGIC_X0Y145 CLOCKREGION_X0Y3)    Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat    aSer/SerialGen[3].SlaveOserdes (Locked Site: OLOGIC_X0Y158 CLOCKREGION_X0Y3)    Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat    aSer/SerialGen[5].MasterOserdes (Locked Site: OLOGIC_X0Y107 CLOCKREGION_X0Y2)    Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat    aSer/SerialGen[0].SlaveOserdes (Locked Site: OLOGIC_X0Y132 CLOCKREGION_X0Y3)    Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat    aSer/SerialGen[9].MasterOserdes (Locked Site: OLOGIC_X0Y105 CLOCKREGION_X0Y2)    Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat INFO:TclTasksC:1850 - process run : Map is done.    aSer/SerialGen[8].SlaveOserdes (Locked Site: OLOGIC_X0Y112 CLOCKREGION_X0Y2)    Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat    aSer/SerialGen[2].MasterOserdes (Locked Site: OLOGIC_X0Y155 CLOCKREGION_X0Y3)    Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat    aSer/SerialGen[5].SlaveOserdes (Locked Site: OLOGIC_X0Y106 CLOCKREGION_X0Y2)    Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat    aSer/SerialGen[6].MasterOserdes (Locked Site: OLOGIC_X0Y97 CLOCKREGION_X0Y2)    Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat    aSer/SerialGen[2].SlaveOserdes (Locked Site: OLOGIC_X0Y154 CLOCKREGION_X0Y3)    Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat    aSer/SerialGen[3].MasterOserdes (Locked Site: OLOGIC_X0Y159 CLOCKREGION_X0Y3)    Please evaluate the location constraints of both the BUFIO and the components    driven by    to    ensure that they follow the clock region rules of the architecture. For more    information on the clock region rules, please refer to the architecture    user's guide. To debug your design with partially routed design, please allow    mapper/placer to finish the execution (by setting environment variable    XIL_PAR_DEBUG_IOCLKPLACER to 1).
Phase 7.2  Initial Clock and IO Placement (Checksum:a3d3c539) REAL time: 1 mins 35 secs
Total REAL time to Placer completion: 1 mins 35 secs Total CPU  time to Placer completion: 59 secs ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
Mapping completed. See MAP report file "Puma20Top_map.mrp" for details. Problem encountered during the packing phase.
Design Summary -------------- Number of errors   :   2 Number of warnings : 442
Process "Map" failed

Thank you very much for your help.

Regards,
Denis.
            NI6587ConnectorSerdesOLED.zip ‏31 KB

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