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我目前正在研究STM8L052C6项目,我希望在端口C引脚上设置一些中断。查看数据表中的引脚说明
http://www.st.com/resource/en/datasheet/stm8l052c6.pdf ,似乎端口C引脚应该能够配置为外部中断。但是,从同一文档查看中断表不会显示端口C的任何条目。但是,它确实包含与端口G和H关联的条目,这两个条目在此特定软件包上都不存在。因此,数据表中似乎存在错误。请注意,在STM8L052C6芯片上将端口C引脚配置为外部中断?如果是这样,使用的IRQ号码是多少? #interrupts#stm8l052c6 以上来自于谷歌翻译 以下为原文 I'm currently working on an STM8L052C6 project, and am looking to set up some interrupts on Port C pins. Looking at the pin description in the datasheet http://www.st.com/resource/en/datasheet/stm8l052c6.pdf , it appears that Port C pins should be capable of being configured as external interrupts. However, looking at the interrupt table from the same document does not show any entry for Port C. However, it does contain entries associated with Port G and H, both of which do not exist on this particular package. So it appears there is an error in the datasheet.With this in mind, is configuring Port C pins as external interrupts possible on the STM8L052C6 chip? If so, what is the proper IRQ number to use? #interrupts #stm8l052c6 |
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看来我的答案可能在STM8L052C6参考手册的第12.6节中:
12.6外部中断 11个中断向量专用于外部中断事件: • 端口B或G上的EXTIB / G - 8行:PB [7:0]或PG [7:0] EXTID / H - 端口D或H上的8行: PD [7:0]或PH [7:0] • 端口E或F上的EXTIE / F - 8行:PE [7:0]或PF [7:0] • EXTI0 - 端口A / B / C / D / E / F上的6行,位0:Px [0] • EXTI1 - 端口A / B / C / D / E上的5行,位1:Px [1] • EXTI2 - 端口A / B / C / D / E上的5行,位2:Px [2] • EXTI3 - 端口A / B / C / D / E上的5行,第3位:Px [3] • EXTI4 - 端口A / B / C / D / E上的5行,第4位:Px [4] • EXTI5 - 端口A / B / C / D / E上的5行,第5位:Px [5] • EXTI6 - 端口A / B / C / D / E上的5条线,位6:Px [6] • EXTI7 - 端口A / B / C / D / E上的5条线,第7位:Px [7] 所以看起来我会将EXTI0用于PC0,EXTI1用于PC1等,并且使用EXTIB / G和EXTID / H代替EXTIB和EXTID的模糊性是有意的,因此相同的文档可以应用于STM8L052系列中的所有芯片。 在这种情况下,似乎数据表中没有错误,只是一些模糊性需要仔细检查才能澄清。为虚警道歉。 以上来自于谷歌翻译 以下为原文 It appears that my answer may be in section 12.6 of the STM8L052C6 reference manual: 12.6 External interrupts Eleven interrupt vectors are dedicated to external Interrupt events: • EXTIB/G - 8 lines on Port B or G: PB[7:0] or PG[7:0]EXTID/H - 8 lines on Port D or H: PD[7:0] or PH[7:0] • EXTIE/F - 8 lines on Port E or F: PE[7:0] or PF[7:0] • EXTI0 - 6 lines on Port A/B/C/D/E/F, bit 0: Px[0] • EXTI1 - 5 lines on Port A/B/C/D/E, bit 1: Px[1] • EXTI2 - 5 lines on Port A/B/C/D/E, bit 2: Px[2] • EXTI3 - 5 lines on Port A/B/C/D/E, bit 3: Px[3] • EXTI4 - 5 lines on Port A/B/C/D/E, bit 4: Px[4] • EXTI5 - 5 lines on Port A/B/C/D/E, bit 5: Px[5] • EXTI6 - 5 lines on Port A/B/C/D/E, bit 6: Px[6] • EXTI7 - 5 lines on Port A/B/C/D/E, bit 7: Px[7] So it appears that I would use EXTI0 for PC0, EXTI1 for PC1, etc. and the ambiguity of using EXTIB/G and EXTID/H instead of EXTIB and EXTID is intentional so that the same documentation can apply to all chips in the STM8L052 family. In this case, it appears that there is no error in the datasheet, just some ambiguity that requires careful inspection to clarify. Apologies for the false alarm. |
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