信号被删除的麻烦

只是澄清一下，信号（不是“引脚”）已被删除。
“引脚”是指FPGA封装引脚，而不是内部信号。
如何产生信号S0和S1？
是否删除了其他信号？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
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以下为原文

Just a clarification, signals (not "pins") have been removed.  "Pins" refer to FPGA package pins, not internal signals.
 
How are the signals S0 and S1 generated?
Are any other signals deleted?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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好吧，如果你看一下原始文章中的图片，s1和s0分布在整个多路复用原理图中，然后分布在顶部原理图中。信号映射到Basys2 250k FPGA上的2个开关。



以下为原文

Well if you look at the pictures in the original post, the s1 and s0 are distributed throughout the mux schematic and then in the top schematic.

The signal is mapped to 2 switches on the Basys2 250k FPGA.

信号映射到Basys2 250k FPGA上的2个开关。
这是我在第一个问题中寻求的信息。
一般来说，XST删除信号有三个原因：
信号没有来源
信号源，或由没有（有效）时钟的触发器提供
信号没有负载（即驱动逻辑也被删除）
这是最后一个案例，它提示我的另一个问题（尚未答复）：还删除了哪些其他信号？
另一个调试建议：在合成之前检查从原理图生成的网表，并验证删除的信号是否在网表中正确连接到设备引脚。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

The signal is mapped to 2 switches on the Basys2 250k FPGA.
 
This is the information I was seeking in my first question.
 
There are three reasons, generally, that XST deletes signals:

• Signal has no source
  
• Signal sources, or is sourced by, a flip-flop with no (valid) clock
  
• Signal has no load (i.e. drives logic which has also been deleted)
  

It is this last case which prompts my other question (yet unanswered):  what other signals have been deleted?
 
Another debugging suggestion:  Check the netlist generated from the schematics, before synthesis, and verify that the deleted signals are properly connected in the netlist to the device pins.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.