完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
尝试运行CORDIC代码时遇到错误,该代码表示:
error1:Pack:2309 - 找到太多类型为“IBUF”的绑定组件适合此设备。 error2:Pack:18 - 对于给定的设备和包,设计太大。 请查看“设计摘要”部分,了解设计的哪个资源要求超出了设备中可用的资源。 我看到了设计摘要:“保税IOB数量”的利用率为121%,其他低于100%。 这是什么意思,我该如何纠正呢? 我附上了我所指的论文,代码如下 模块cordic(z0,x0,y0,xn,yn,en);输入有符号[15:0] z0,x0,y0;输入en;输出有符号[15:0] xn,yn; reg [15:0] xn ,yn;参数[3:0] iter = 4'd14; reg签署[15:0] thetai; reg [3:0] ii = 0; reg [3:0] i; reg签署[15:0] zi ,xi,yi,xtemp,ytemp; reg di; reg [15:0] pi = 16'b0110010010000111; reg [15:0] pi2 = 16'b0011001001000011;总是@(en)beginif(z0 [15] == 0 )beginif(z0 [14:13]> 2'd1)beginxi = 0-y0; yi = x0; zi = z0-pi2; endelsebeginxi = x0; yi = y0; zi = z0; endendelse if(z0 [15] = = 1)beginif(Z0 [14:13]> 2'd1)beginxi = Y0; YI = 0-X0;滋= Z0 + PI2; endelsebeginxi = X0; YI = Y0;滋= Z0; endendxn = 0;炔= 0;对于(II = 0; iibeginytemp =(YI >>>ⅱ); xtemp =(XI >>>ⅱ);如果(ZI [15] == 0)beginxn = XI-ytemp;炔=义+ xtemp; 滋=滋thetai [II]; endelsebeginxn = XI + ytemp;炔=苡xtemp;滋=滋+ thetai [II]; endxi = XN; YI =炔; //结束XN = XN /一种; //炔 = YN / AN; endendmodule 可扩展流水线CORDIC架构设计.pdf 667 KB 以上来自于谷歌翻译 以下为原文 I got an error while trying to run CORDIC code which said: error1: Pack:2309 - Too many bonded comps of type "IBUF" found to fit this device. error2: Pack:18 - The design is too large for the given device and package. Please check the Design Summary section to see which resource requirement for your design exceeds the resources available in the device. I saw the Design summary: the percentage utilization of "number of bonded IOBs" is 121%, others are below 100%. what does this mean and how can I correct it? I have attached the paper I am referring and the code is as follows module cordic(z0,x0,y0,xn,yn,en); input signed [15:0]z0,x0,y0; input en; output signed [15:0]xn,yn; reg [15:0]xn,yn; parameter [3:0]iter=4'd14; reg signed [15:0]thetai; reg [3:0]ii=0; reg [3:0]i; reg signed [15:0]zi,xi,yi,xtemp,ytemp; reg di; reg [15:0]pi=16'b0110010010000111; reg [15:0]pi2=16'b0011001001000011; always @(en) begin if(z0[15]==0) begin if(z0[14:13]>2'd1) begin xi=0-y0; yi=x0; zi=z0-pi2; end else begin xi=x0; yi=y0; zi=z0; end end else if(z0[15]==1) begin if(z0[14:13]>2'd1) begin xi=y0; yi=0-x0; zi=z0+pi2; end else begin xi=x0; yi=y0; zi=z0; end end xn=0; yn=0; for(ii=0;ii ytemp=(yi>>>ii); xtemp=(xi>>>ii); if(zi[15]==0) begin xn=xi-ytemp; yn=yi+xtemp; zi=zi-thetai[ii]; end else begin xn=xi+ytemp; yn=yi-xtemp; zi=zi+thetai[ii]; end xi=xn; yi=yn; end //xn=xn/An; //yn=yn/An; end endmodule Scalable Pipelined CORDIC Architecture Design.pdf 667 KB |
|
相关推荐
6个回答
|
|
尝试运行CORDIC代码时遇到错误,该代码表示:
error1:Pack:2309 - 找到太多类型为“IBUF”的绑定组件适合此设备。 error2:Pack:18 - 对于给定的设备和包,设计太大。 请查看“设计摘要”部分,了解设计的哪个资源要求超出了设备中可用的资源。 我看到了设计摘要:“保税IOB数量”的利用率为121%,其他低于100%。 这是什么意思,我该如何纠正呢? 我附上了我所指的论文,代码如下 模块cordic(z0,x0,y0,xn,yn,en);输入有符号[15:0] z0,x0,y0;输入en;输出有符号[15:0] xn,yn; reg [15:0] xn ,yn;参数[3:0] iter = 4'd14; reg签署[15:0] thetai; reg [3:0] ii = 0; reg [3:0] i; reg签署[15:0] zi ,xi,yi,xtemp,ytemp; reg di; reg [15:0] pi = 16'b0110010010000111; reg [15:0] pi2 = 16'b0011001001000011;总是@(en)beginif(z0 [15] == 0 )beginif(z0 [14:13]> 2'd1)beginxi = 0-y0; yi = x0; zi = z0-pi2; endelsebeginxi = x0; yi = y0; zi = z0; endendelse if(z0 [15] = = 1)beginif(Z0 [14:13]> 2'd1)beginxi = Y0; YI = 0-X0;滋= Z0 + PI2; endelsebeginxi = X0; YI = Y0;滋= Z0; endendxn = 0;炔= 0;对于(II = 0; iibeginytemp =(YI >>>ⅱ); xtemp =(XI >>>ⅱ);如果(ZI [15] == 0)beginxn = XI-ytemp;炔=义+ xtemp; 滋=滋thetai [II]; endelsebeginxn = XI + ytemp;炔=苡xtemp;滋=滋+ thetai [II]; endxi = XN; YI =炔; //结束XN = XN /一种; //炔 = YN / AN; endendmodule 以上来自于谷歌翻译 以下为原文 I got an error while trying to run CORDIC code which said: error1: Pack:2309 - Too many bonded comps of type "IBUF" found to fit this device. error2: Pack:18 - The design is too large for the given device and package. Please check the Design Summary section to see which resource requirement for your design exceeds the resources available in the device. I saw the Design summary: the percentage utilization of "number of bonded IOBs" is 121%, others are below 100%. what does this mean and how can I correct it? I have attached the paper I am referring and the code is as follows module cordic(z0,x0,y0,xn,yn,en); input signed [15:0]z0,x0,y0; input en; output signed [15:0]xn,yn; reg [15:0]xn,yn; parameter [3:0]iter=4'd14; reg signed [15:0]thetai; reg [3:0]ii=0; reg [3:0]i; reg signed [15:0]zi,xi,yi,xtemp,ytemp; reg di; reg [15:0]pi=16'b0110010010000111; reg [15:0]pi2=16'b0011001001000011; always @(en) begin if(z0[15]==0) begin if(z0[14:13]>2'd1) begin xi=0-y0; yi=x0; zi=z0-pi2; end else begin xi=x0; yi=y0; zi=z0; end end else if(z0[15]==1) begin if(z0[14:13]>2'd1) begin xi=y0; yi=0-x0; zi=z0+pi2; end else begin xi=x0; yi=y0; zi=z0; end end xn=0; yn=0; for(ii=0;ii ytemp=(yi>>>ii); xtemp=(xi>>>ii); if(zi[15]==0) begin xn=xi-ytemp; yn=yi+xtemp; zi=zi-thetai[ii]; end else begin xn=xi+ytemp; yn=yi-xtemp; zi=zi+thetai[ii]; end xi=xn; yi=yn; end //xn=xn/An; //yn=yn/An; end endmodule |
|
|
|
首先 - CORDIC核心是您的顶级设计模块是不寻常的。
为什么是 你通过地图运行这个? 第二 - 错误似乎很清楚,你所针对的设备不够用 用于处理所有输入和输出的引脚。 我统计了81个顶级端口。 什么设备 你正在瞄准目标,是否有81个IO可用? - Gabor - Gabor 以上来自于谷歌翻译 以下为原文 First - it is unusual that a CORDIC core would be your top level design module. Why are you running this through map? Second - the error seems clear enough, the device you targetted does not have enough pins to handle all of your inputs and outputs. I counted 81 top level ports. What device and package are you targetting, and does it have 81 IO's available? -- Gabor -- Gabor |
|
|
|
我相信你会使用一个小型S3衍生设备,只有IBUF类型的打击垫。
我相信你的设备中的可用输入已经用尽,但仍有可用的输出。 还只是日志,看看是否其他东西实际上失败了。 有时,当发生错误时,工具将无法完成对设备的打包,并且通常不会为IO提供错误的错误。 要测试核心,您可以在综合期间禁用IO插入,然后在NGDBUILD和MAP中使用-u选项来修剪掉未使用的逻辑(不附加到IO),也就是说,如果您只是想看一下 错误是。 或者你可以选择更大的设备。 以上来自于谷歌翻译 以下为原文 I believe you would be using a small S3 derivative device where there are IBUF only type pads. I believe you have run out of the available inputs in the device while there still may be available outputs. Also just the log to see if something else actually failed. Sometimes the tools will not finish packing the device when an error occurs and will give you a false error though not usually for IOs. To test the core you can disable IO insertion during synthesis and then use the -u option in NGDBUILD and MAP to not trim out the unused logic (not attached to an IO), that is if you just want to get a look at what the error is. Or you can choose a bigger device. |
|
|
|
设备是斯巴达3E XC3S100E。错误是什么意思?
我怎么能纠正它? 这实际上用于电机控制中的停车改造。 但是现在我只想尝试实现cordic模块。 以上来自于谷歌翻译 以下为原文 device is spartan 3E XC3S100E. what does the error mean? how can I correct it? this is actually used for park transformation in motor control. but right now i am just trying to implement cordic module. |
|
|
|
我怎么能压缩代码。
实际上有更多的模块要实现,如果我不能适应这个设备,你能建议我应该使用哪一个? 以上来自于谷歌翻译 以下为原文 how can i compress the code. actually there are are many more modules to be implemented, if i am not able to fit them in this device, can you suggest me which one should i use? |
|
|
|
为什么不在一个论坛中选择一个帖子来继续这个主题。
您是否希望我们阅读并发布到此主题或其他主题? - 鲍勃埃尔金德 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 以上来自于谷歌翻译 以下为原文 Why don't you pick one thread in one forum to continue this topic. Do you want us to read and post to this thread, or the other thread ? -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
|
|
|
只有小组成员才能发言,加入小组>>
2423 浏览 7 评论
2824 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2294 浏览 9 评论
3374 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2465 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
1192浏览 1评论
请问vc707的电源线是如何连接的,我这边可能出现了缺失元件的情况导致无法供电
590浏览 1评论
求一块XILINX开发板KC705,VC707,KC105和KCU1500
452浏览 1评论
2006浏览 0评论
731浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-12-24 07:32 , Processed in 1.433562 second(s), Total 88, Slave 71 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号