有没有办法在ISE中设置Include目录？

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ISE Processes窗格 -  Synthesis-XST  - 右键单击​​Properties  -  Synthesis Options  -  Verilog Include Directories。
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以下为原文

Found it! ISE Processes pane - Synthesis-XST - right-click Properties - Synthesis Options - Verilog Include Directories.
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找到了！
ISE Processes窗格 -  Synthesis-XST  - 右键单击​​Properties  -  Synthesis Options  -  Verilog Include Directories。



以下为原文

Found it! ISE Processes pane - Synthesis-XST - right-click Properties - Synthesis Options - Verilog Include Directories.

ISE 10.1的另一点是您可以“切换路径”以在完整路径名之间切换
和相对于项目目录的路径。
我通常使用相对路径来允许项目
通过简单地复制包含它的整个目录结构来复制。
通常我有
一个带有项目名称的容器目录，在其下面我有源目录，
模拟，核心和ISE。
然后，ISE子目录就是“项目”目录
由ISE导航器和它的所有中间文件存储在那里，而不是污染
源文件结构。
然后我的来源将看起来像“../source/blah.v”
似乎路径切换的当前状态将影响路径的存储方式
ISE项目文件。
因此，在关闭项目之前，我确保路径是相对的。
-  Gabor
-  Gabor



以下为原文

Another point with ISE 10.1 is that you can "toggle paths" to switch between full path names
and paths relative to the project directory.  I normally use relative paths to allow the project
to be copied by simply copying the entire directory structure containing it.  Normally I have
a container directory with the project name, and under that I have directories for source,
simulation, cores, and ISE.  The ISE subdirectory is then the "project" directory as seen
by the ISE navigator and all of its intermediate files are stored there, rather than polluting
the source file structure.  Then my sources will look like "../source/blah.v"
 
It seems that the current state of the paths toggle will affect the way paths are stored in
the ISE project file.  So I make sure that the paths are relative before closing the project.
 
-- Gabor
-- Gabor

感谢Gabor的建议。
问候，
保罗



以下为原文

Thanks for the advice, Gabor.
Regards,
Paul