有在PSOS4中实现两个SPI外设相互通信的例子代码吗？

我不明白你为什么会想要两SPI模块在同一芯片上互相交谈…
总之，我把它用于创建两个SPI设备相互通信的镜头，和钳工不会路由到彼此的电线。
不确定的IDE会让你丝的SPI接口在内部。



     以下为原文
  I don't understand why you would want the two SPI modules on the same chip talking to each other...
Anyhow, I gave it a shot for creating two SPI devices communicating with each other, and the fitter won't route the wires to each other.
Not sure the IDE will let you wire the SPIs together internally.

我要用两斯皮思互相交谈，因为我想测试psoc4的SPI和我规划我psoc4做SPI和我只有一套，42xx CY8CKIT-049。我没有工具的程序员，所以我的编程工具通过bootloadable和UART组件的方法。无论是使用UDB还是SCB SPI，在两种情况下都会出错。这错误主要产生因为我使用三串行通信通道，因此钟。（随信附上与SCB SPI错误快照。）我目前面临的问题是我不能理解的错误传达有不多详细信息给出了LS。我需要帮助解决这些错误。还有，谁能帮我理解组件的目录（在创造者）对不同设备的柏树。
提前感谢。
夏纳克阿加斯塔维亚斯
HTTPS://TiNUILIVE/



     以下为原文
  I have to use two SPIs talking to each other because I want to test PSoC4's SPI with my programming as I am doing SPI with PSoC4 and I have only one kit that is CY8CKIT-049 42xx. I do not have kit programmer, so I am programming the kit through the Bootloadable and UART Component Method. Whether I use UDB or SCB SPI, I get errors in both cases. This errors mainly generate because I am using three serial communication channels and hence clocks.(Please find attached herewith the snapshot of errors with SCB SPI.) The problem I am facing currently is I am not able to understand the messages the errors are conveying as there are not much details given. I need help in resolving these errors. Also, can someone help me to understand the component catalog (Given in Creator) of Cypress for different devices.
 

Thanks in advance.
 
Shaunak Agastya Vyas
https://tinu.live/

你好，夏纳克，
错误的图像你张贴表明只有两个SPI外设，但你正在使用，因此它不能建设。
同时，它需要更多的时钟工作清单；如果你打开组件和设置时钟是外部的，然后创建一个“时钟”组件的示意图并将其连接到所有的SPI设备可以解决太多问题的输入时钟”。



     以下为原文
  Hello Shaunak,
 
The errors in the image you posted show that there are only two SPI peripherals, but you are trying to use 3, and thus it can't build it.
Also, it is listing as needing more clocks to work; If you open the component and set the clock to be external, then create a "Clock" component on the schematic and wire it to the inputs of all of the SPI devices you might be able to fix the "too many clocks" issue.

嗨·E·普拉特
随信附上一张快照。我恳请您查看顶部设计和错误。你能解释它是如何计算7状态细胞代替呢？
提前感谢。
夏纳克阿加斯塔维亚斯
HTTPS://TiNUILIVE/



     以下为原文
  Hi e.pratt
Please find attached herewith a snapshot. I kindly request you to see the TopDesign and Errors. Can you please explain how it is counting 7 Status Cells instead of 4?
 
Thanks in advance.
 
Shaunak Agastya Vyas
https://tinu.live/
 

你好，夏纳克，
状态单元计数与使用Verilog实现硬件功能的通用电路UDB（用户定义块）有关。SPI组件利用这些UDB块来实现SPI功能，而不使用CPU时间/软件代码。
每个IC在工厂中内置的UDB数量有限，并且基于特定芯片。你设计的芯片只有4个作为状态单元的UDB。附图显示了您可以在这方面查看当前硬件资源的项目使用情况。
本质上，SPI模块使用3个单元，UART可能使用1个单元。但你应该能够看到成功的项目建设与外围设备包括在内。
有多个SPI外围模块被定义，其中一些可能使用较少的UDB单元（我不知道哪一个，如果有的话）。
PNG
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     以下为原文
  Hello Shaunak,
 
The status cell count is related to the UDB (User Defined Block) which are general purpose circuitry used to implement hardware functions using verilog. The SPI components utilize theses UDB blocks to realize the SPI functionality without using CPU time/software code.
Each IC has a limited number of UDBs built into it at the factory, and the number is based on the specific chip. The chip you are designing for only has 4 UDBs that are Status Cells. The attached picture shows where you can look at the current project usage of the hardware resources in this respect.
Essentially, the SPI modules use 3 cells each, and the UART probably uses 1. But you should be able to see upon successful project build with the peripherals included.
There are multiple SPI peripheral modules defined, some of them may use less UDB cells (I have no idea which, if any, do)

•   Status_Cells_Count.PNG 31.9 K