次优逻辑布局失败

我想与Virtex-6 LX130T设计ISE13.1工具中的次优逻辑布局分享我的挫败感。
时钟频率为300MHz的外部总线进入FPGA。
所有输入都放在IOB中，然后使用2个触发器流水线直到它们到达目的地：
ext总线 - > IOB  - > FF（1） - > FF（2） - >目标FF
我希望这些工具可以放置这两个触发器，使它们在输入和目标之间均匀分布。
通常是这种情况，但不是像这样一个高度利用和拥挤的设计。我看到的是IOB和FF（1）之间的长路线，它失败了时间，FF（1）和FF之间的路线很短（
2）。
我尝试使用“INST my_flop LOC = SLICE_X＃Y＃”约束在正确的位置手动布局规划这些触发器。这种方法有效，但这样做至少有两个缺点：
- 需要手动布局规划几十个人字拖
- 设计变得不那么便携，因为我需要确保逻辑和名称保持不变。
我还确保它没有作为SRL进行优化，并尝试了不同的重置方案和MAP选项。
任何想法为什么会发生，还有什么可以尝试？
谢谢，
叶夫根



以下为原文

I want to share my frustration with a sub-optimal logic placement in Virtex-6 LX130T design, ISE13.1 tools.

There is an external bus clocked at 300MHz coming into an FPGA. All the inputs are placed in IOB and then pipelined using 2 flops until they reach the destination:
    ext bus -> IOB -> FF(1) -> FF(2) -> destination FF

I'd expect the tools will place those two flops such that they're evenly spaced between the input and destination.  Usually this is the case, but not in a highly utilized and congested design like this one. What I see is a long route between IOB and FF(1), which fails timing, and very short route between FF(1) and FF(2).

I've tried manually floorplanning those flops in the right places using "INST my_flop LOC = SLICE_X#Y#" constraint. This approach works, but there are at least two disadvantages of doing that:
  - need to manually floorplan dozens of flops
  - the design becomes less portable, because I need to make sure to keep the logic and names intact.

I also made sure that it's not optimized as SRL, and experimented with different reset schemes and MAP options.

Any ideas why it happens and what else to try ?

Thanks,
Evgeni