dsPIC33FJ32MC304：SPIxCON1.SPRE <2：0>混淆

DSPIC33 FRM部分18（DS7000 05185A）给出了SPIXCON1.SPRE的以下描述：111＝次级预分频器1:1110＝次级预分频2:1…000＝次级预分频8:1，那么未写入的预分频值是什么？3:1，4:1，5:1，6:1，7:1？我发现有点奇怪，质数值如3:1、5:1、7:1是可用的时钟除法器选项。这些真的可用吗？我问，因为我正试图实现4兆赫SPI时钟从40兆赫FCY。如果上述假设是正确的，这是不可能的。最接近的值是：5 MHz，PPRE＝2（4:1），SPRE＝6（2:1），这太快了。或3.33兆赫与PPRE＝2（4:1），SPRE＝5（3:1），如果存在这样的选项。令人烦恼的是，这不是4兆赫。



      以下为原文

    dsPIC33 FRM section 18 (DS70005185A) gives the following description of SPIxCON1.SPRE:

111 = Secondary prescale 1:1
110 = Secondary prescale 2:1
.
.
.
000 = Secondary prescale 8:1

So what are the unwritten prescale values? 3:1, 4:1, 5:1, 6:1, 7:1?

I find it a bit strange that prime number values like 3:1, 5:1, 7:1 are available clock divider options. Are these really available?

I ask because I'm trying to achieve 4 MHz SPI clock from 40 MHz Fcy. This does not appear possible if above assumptions are correct. Closest values would be: 5 MHz with PPRE = 2 (4:1), SPRE = 6 (2:1) -- this is too fast. Or 3.33 MHz with PPRE = 2 (4:1), SPRE = 5 (3:1), if such option exists. Annoyingly, this is not desired 4 MHz.