约束路由以不通过CLB路由

我会使用RPM宏和定向路由（DIRT）约束的组合来执行此操作。
在FPGA编辑器中捕获的DIRT约束是可以重用于多个宏实例的相对约束。
成功使用DIRT约束的关键是确保网络的相对引脚位置得到精确控制，并确保RPM宏的位置。除了定义宏的RLOC约束外，还可能需要使用BEL约束来控制BEL
切片内的位置和LOCK_PINS约束来控制LUT引脚的使用
回到硬宏，我不明白这个需要。
您希望通过禁止使用某些路由资源来实现什么目标？
但如果您仍想这样做，您将在FPGA编辑器中创建一个硬宏。
宏将是自包含的，所有驱动程序和加载引脚都是宏的一部分，并且路由利用您希望阻止设计使用的路由资源。
您的设计将无法使用宏使用的任何切片位置。
在原帖中查看解决方案



以下为原文

I would use a combination of RPM macros and Directed Routing (DIRT) constraints to do this. The DIRT constraints which are captured in FPGA Editor are relative constraints that can be reused for multiple macro instantiations. The key to successfully using DIRT constraints is ensuring that the relative pin locations for the nets are exactly controlled and that's where the RPM macro comes in. Besides the RLOC constraints that define the macro, it may also be necessary to use BEL constraints to control BEL location within a slice and LOCK_PINS constraints to control LUT pin usage
 
Getting back to the hard macro, I don't understand the need for this. What do you expect to accomplish by prohibiting the use of certain routing resources? But if you still want to do that, you would create a hard macro in FPGA Editor. The macro would be self contained with all driver and load pins being part of the macro and with routing that utilizes the routing resources that you want to prevent your design from using. Your design will not be able to use any of the slice locations that are used by the macro.
View solution in original post

不存在可用于路由的禁止约束。
可以应用专家用户技巧，即创建虚拟硬宏，使用您希望阻止PAR路由器使用的路由资源。
这会强制PAR路由器执行其他操作。
你想要准确地阻止什么？
可能还有其他方式。



以下为原文

No there is no prohibit constraint that can be used for  routing. There is an expert-user trick that can be applied which is to create a dummy hard macro that uses the routing resource that you want to prevent the PAR router from using. This forces the PAR router to do something else. What are you trying to prevent exactly? There may be other ways.

我听说创建了一个硬宏，它占用了CLB的所有路由，然后让PAR路由剩下的设计。
我想我在会议的一个摊位上看到了这么难的宏......我如何创建这样一个虚拟的硬宏？
xdl -report -all_conns将为我提供整个设备的所有路由信息。我可以理解（虽然不完全令我满意）pip连接..如何从这创建一个虚拟硬宏？
或者我是否必须使用FPGA编辑器？....能否请您提供一个示例..这对我来说将是一个很大的帮助
基本上我有一个我需要复制的设计，我需要将复制设计放在原始设计旁边...以一种网状方式。
例如，如果CLB_X3Y5包含原始设计，那么它的直接右边CLB将包含与CLB_X3Y5完全匹配的路由的重复部分。
我希望你有意义
非常感谢。
干杯，拉吉



以下为原文

I heard about creating a hard macro which uses up all the routing of a CLB and then lets PAR route the remaining design..
I think I saw the such a hard macro in one of the stalls at a conference....How do i create such a dummy hard macro?..
 
xdl -report -all_conns will give me all the routing information of the entire device..And i can understand (although not completely to my satisfaction) the pip connections..how do i create a dummy Hard macro from this? or do i have to use FPGA Editor?....Can you please provide me an example..it will be a great help to me
 
Basically i have a design which i need to duplicate and i need to place the duplicate design right next to the original one...in a kind of meshed fashion. for example if CLB_X3Y5 contains the original design then its immediate right CLB will contain duplicate part with completely matched routing as that of CLB_X3Y5 ..
I hope it make sense to you
 
Thanks a lot.
 
 
Cheers,
Raj

我会使用RPM宏和定向路由（DIRT）约束的组合来执行此操作。
在FPGA编辑器中捕获的DIRT约束是可以重用于多个宏实例的相对约束。
成功使用DIRT约束的关键是确保网络的相对引脚位置得到精确控制，并确保RPM宏的位置。除了定义宏的RLOC约束外，还可能需要使用BEL约束来控制BEL
切片内的位置和LOCK_PINS约束来控制LUT引脚的使用
回到硬宏，我不明白这个需要。
您希望通过禁止使用某些路由资源来实现什么目标？
但如果您仍想这样做，您将在FPGA编辑器中创建一个硬宏。
宏将是自包含的，所有驱动程序和加载引脚都是宏的一部分，并且路由利用您希望阻止设计使用的路由资源。
您的设计将无法使用宏使用的任何切片位置。



以下为原文

I would use a combination of RPM macros and Directed Routing (DIRT) constraints to do this. The DIRT constraints which are captured in FPGA Editor are relative constraints that can be reused for multiple macro instantiations. The key to successfully using DIRT constraints is ensuring that the relative pin locations for the nets are exactly controlled and that's where the RPM macro comes in. Besides the RLOC constraints that define the macro, it may also be necessary to use BEL constraints to control BEL location within a slice and LOCK_PINS constraints to control LUT pin usage
 
Getting back to the hard macro, I don't understand the need for this. What do you expect to accomplish by prohibiting the use of certain routing resources? But if you still want to do that, you would create a hard macro in FPGA Editor. The macro would be self contained with all driver and load pins being part of the macro and with routing that utilizes the routing resources that you want to prevent your design from using. Your design will not be able to use any of the slice locations that are used by the macro.

嗨，
我一直试图保存我的DIRT约束，然后移动宏
周围。
我不断收到'确切路由不是'的消息
当我向右移动组件4个空格时可以实现 
RPM_GRID（即从RLOC X0Y0到X4Y0）。
但是，我可以做到这一点
使用FPGA编辑器路由。
在转变之前，这是我的UCF。
NET“c”ROUTE =“{3; 1; 5vlx110tff1136; d760ba8a！-1; -57504; -226536; S！0; 0; -8！1; -683;”“ -  152！2; -1949; 8819
！2; 0; 192 4;！683; -88; L}！ “;＃ROUTE =”{3; 1; 5vlx110tff1136;！36e466c2 -1; -116400; -259560; S 0;！0; -8！
1; -683;“＃” -  152！2; -1949; 8819！2; 0; 192！4; 683; -88; L！}“; NET”c“U_SET =”f“; #I's
读到这是非法的，但我仍然尝试过。
我没有收到此INST的错误或警告“LUT5_inst2”RLOC = X10Y0;
＃移动路由组件INST“LUT5_inst2”RPM_GRID = GRID; INST“LUT5_inst2”U_SET =“f”; INST“FDCPE_inst”RLOC = X0Y0; INST“FDCPE_inst”U_SET =“f”; INST“LUT5_inst2”BEL =“D6LUT”
; #INST“FDCPE_inst”RLOC_ORIGIN = X11Y0;
＃我也想从角落开始，但是当我这样做时，工具会删除我的网
请注意，路线是天线。
我这样做
故意为研究思路。
我还在努力。
有什么建议么
会很高兴。
问候，
Sudhanshu



以下为原文

Hi,
I've been trying to save my DIRT constraints and then move the macro around. I keep getting the message that the 'exact routing was not possible to implement when I move the component 4 spaces to the right on the RPM_GRID (that is from RLOC X0Y0 to X4Y0). But, I can make this route using FPGA editor. here's my UCF before the shift.
 
NET "c"
ROUTE="{3;1;5vlx110tff1136;d760ba8a!-1;-57504;-226536;S!0;0;-8!1;-683;"
"-152!2;-1949;8819!2;0;192!4;683;-88;L!}";
#ROUTE="{3;1;5vlx110tff1136;36e466c2!-1;-116400;-259560;S!0;0;-8!1;-683;"
#"-152!2;-1949;8819!2;0;192!4;683;-88;L!}";
NET "c" U_SET="f";# I've read that this is illegal but I still tried it. I don't get an error or warning for this.
INST "LUT5_inst2" RLOC=X10Y0; #To move the routed component
INST "LUT5_inst2" RPM_GRID=GRID;
INST "LUT5_inst2" U_SET="f";
INST "FDCPE_inst" RLOC=X0Y0;
INST "FDCPE_inst" U_SET="f";
INST "LUT5_inst2" BEL="D6LUT";
#INST "FDCPE_inst" RLOC_ORIGIN = X11Y0; # I want to start from the corner too but the tool removes my net when I do this
 
Please note that the route is an antenna. I'm doing that intentionally for a research idea. I'm still working on this. Any suggestions would be highly appretiated.
 
regards,
Sudhanshu

嗨，
我一直试图保存我的DIRT约束，然后移动宏
周围。
我不断收到'确切路由不是'的消息
当我向右移动组件4个空格时可以实现 
RPM_GRID（即从RLOC X0Y0到X4Y0）。
但是，我可以做到这一点
使用FPGA编辑器路由。
在转变之前，这是我的UCF。
NET“c”ROUTE =“{3; 1; 5vlx110tff1136; d760ba8a！-1; -57504; -226536; S！0; 0; -8！1; -683;”“ -  152！2; -1949; 8819
！2; 0; 192 4;！683; -88; L}！ “;＃ROUTE =”{3; 1; 5vlx110tff1136;！36e466c2 -1; -116400; -259560; S 0;！0; -8！
1; -683;“＃” -  152！2; -1949; 8819！2; 0; 192！4; 683; -88; L！}“; NET”c“U_SET =”f“; #I's
读到这是非法的，但我仍然尝试过。
我没有收到此INST的错误或警告“LUT5_inst2”RLOC = X10Y0;
＃移动路由组件INST“LUT5_inst2”RPM_GRID = GRID; INST“LUT5_inst2”U_SET =“f”; INST“FDCPE_inst”RLOC = X0Y0; INST“FDCPE_inst”U_SET =“f”; INST“LUT5_inst2”BEL =“D6LUT”
; #INST“FDCPE_inst”RLOC_ORIGIN = X11Y0;
＃我也想从角落开始，但是当我这样做时，工具会删除我的网
请注意，路线是天线。
我这样做
故意为研究思路。
我还在努力。
有什么建议么
会很高兴。
问候，
Sudhanshu



以下为原文

Hi,
I've been trying to save my DIRT constraints and then move the macro around. I keep getting the message that the 'exact routing was not possible to implement when I move the component 4 spaces to the right on the RPM_GRID (that is from RLOC X0Y0 to X4Y0). But, I can make this route using FPGA editor. here's my UCF before the shift.
 
NET "c"
ROUTE="{3;1;5vlx110tff1136;d760ba8a!-1;-57504;-226536;S!0;0;-8!1;-683;"
"-152!2;-1949;8819!2;0;192!4;683;-88;L!}";
#ROUTE="{3;1;5vlx110tff1136;36e466c2!-1;-116400;-259560;S!0;0;-8!1;-683;"
#"-152!2;-1949;8819!2;0;192!4;683;-88;L!}";
NET "c" U_SET="f";# I've read that this is illegal but I still tried it. I don't get an error or warning for this.
INST "LUT5_inst2" RLOC=X10Y0; #To move the routed component
INST "LUT5_inst2" RPM_GRID=GRID;
INST "LUT5_inst2" U_SET="f";
INST "FDCPE_inst" RLOC=X0Y0;
INST "FDCPE_inst" U_SET="f";
INST "LUT5_inst2" BEL="D6LUT";
#INST "FDCPE_inst" RLOC_ORIGIN = X11Y0; # I want to start from the corner too but the tool removes my net when I do this
 
Please note that the route is an antenna. I'm doing that intentionally for a research idea. I'm still working on this. Any suggestions would be highly appretiated.
 
regards,
Sudhanshu

Sudhanshu，
你用的是什么设备？
定向路由约束是否适用于某些偏移而不适用于其他偏移或是否始终失败？
该约束旨在成为一组用于从引脚到引脚布线的相关指令。
由于没有目标引脚，我希望天线失效。
另外，对网络应用U_SET约束是没有意义的。
宏约束只能应用于实例。



以下为原文

Sudhanshu,
 
What device are you using? Does the Directed Routing constraint work with some offsets and not with others or does it always fail? The constraint is intended to be a set of relative instructions for routing from pin to pin. I would expect it to fail for an antenna since there is no target pin.
 
On a side note, apply U_SET constraints to nets is meaningless. Macro constraints can only be applied to instances.

嗨，
谢谢你的消息。
我正在使用LX110T-1136封装。
我知道网上的U_SET是无用的，但无论如何我试了一下。
是的，我能够编辑DIRT约束以将网络移动到其原始位置的右侧，但不能向左移动。
所以是的，它适用于少数。
那是什么意思？
是否有解决方案以便它始终有效？
还是我犯了错误？
问候，
Sudhanshu



以下为原文

Hi,
Thank you for the message. I'm using an LX110T-1136 package. I am aware that U_SET on a net is useless, but I gave it a try anyway.
 
Yes, I was able to edit the DIRT constraints to move the net to the right of it's original position, but not to the left. So yes it worked for a few. What does that mean? Is there are work-around so that it works all the time? Or am I commiting an error?
 
Regards,
Sudhanshu

可能是因为某些切片可能是SLICEM而不是SLICEL？
如果那是真的那么我将尝试使用奇数SLICE（例如X1Y10，X3Y10等）



以下为原文

Could that be bacause some of the Slices might be SLICEMs instead of SLICELs? If that's true then I'll try to use the odd SLICEs (e.g. X1Y10,X3Y10 etc.)

是的，SLICEM和SLICEL站点之间的路由资源可能有所不同。
这可能就是问题所在。



以下为原文

Yes, the routing resources can vary some between SLICEM and SLICEL sites. That's likely the problem.