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我是盲人但是我可以找到ICAP Spartan-3a的任何时序参数?s3astarterkit设计使用ICAP的分频时钟,所以我假设时钟频率有一些限制我已经看到ICAP在CLK = 66MHz时运行良好但是那里
在配置FPGA但ICAP没有准备好或不接受writeAntti Lukats的情况下,似乎是相当长的启动延迟 以上来自于谷歌翻译 以下为原文 Hi must be I am blind but I can find any timing parameters for the ICAP Spartan-3a? s3astarterkit design uses divided clock for ICAP, so I assume there are some constraints on the clock frequencyOTOH I have seen the ICAP working well with CLK=66MHz but there seems to be rather long startup delay where FPGA is configured but ICAP is not ready or not accepting writes Antti Lukats |
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嘿......我之前遇到过这样的问题,ICAP只是一个内部的Slave SelectMAP端口,所以Slave SelectMAP参数就是你要找的... http://direct.xilinx.com/bvdocs/userguides
/ug332.pdf ...请参阅第163页或第7章......嗯,我认为实际时序数据在数据表中... http://direct.xilinx.com/bvdocs/publications/ds529.pdfpage 56 .HTH! - = G。 ZOD = - 以上来自于谷歌翻译 以下为原文 Hey... I ran into such a problem before, the ICAP is just an internal Slave SelectMAP port, so the Slave SelectMAP parameters is the one you are looking for... http://direct.xilinx.com/bvdocs/userguides/ug332.pdf... look at page 163 or chapter seven... Hmmm, I think the actual timing figures are in the datasheet... http://direct.xilinx.com/bvdocs/publications/ds529.pdf page 56. HTH!!!-=G. ZOD=- |
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嗯,我确实在发布之前阅读了ug332和ds529,在你回复之后我仍然无法找到ICAP时间。我会在早上再读一次,也许我发现他们是安提卢卡特
以上来自于谷歌翻译 以下为原文 Hm, I did read ug332 and ds529 before posting, after your reply and I still cant find the ICAP timing.I will read one more time in the morning, maybe I find them Antti Lukats |
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Hiok我再次重新阅读文档并且我仍然没有看到ICAP时序:(有从属并行时序,是的,但实际上并不一定与内部ICAP时序相同。在一些家庭中我认为ICAP最大频率是
我认为低于最大CCLK,所以我仍然期望在Xilinx文档中给出S3A ICAP时序参数,也可能记录ICAP不接受引导命令时的初始繁忙时间相当长的时间安腾Lukats 以上来自于谷歌翻译 以下为原文 Hi ok I re-read the documents once againand I am still not seing ICAP timings :(there are slave parallel timings, yes, but those are actually not necessarily the same as the internal ICAP timings.on some family I think the ICAP max frequency was lower than max CCLK I think, so I would still expect theS3A ICAP timing parameters being given in Xilinx documentation and maybe also document where there seems to be rather long initial busy time when ICAP would not acceptreboot command Antti Lukats |
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嗨Antti,我也找了ICAP文档和时间,但没有找到任何。我在最新的服务包中更新opb_hwicap外设时需要这些信息。幸运的是,ICAP上的时钟速度并不高,我注册最多
信号.GöranBilski 以上来自于谷歌翻译 以下为原文 Hi Antti, I have also looked for ICAP documentation and timing but haven't found any.I needed this information when I updated the opb_hwicap peripherals in the latest service pack.Fortunately the clock speed on the ICAP is not that high and I registrate most signals. Göran Bilski |
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HiIC(我明白了),好吧那我不是唯一一个;)我有问题,namly picoboot.v无法在spartan3a上运行,当我在配置后立即触发重新配置 - 我认为它与ICAP时钟有关(
什么是66MHz),但后来我测试了50MHz同样的故障,然后问题缩小到另一个未记录的功能,当配置s3a但不接受来自ICAP的重新配置时,必定会有一些“死时间”。 通过用户交互完成重新配置时,无法找到此功能(就像s3a starterkit演示一样)。 但是配置开始重新配置后立即设计将失败,并且因为picoboot.v只启动配置1次,所以我的测试设置不起作用。 在重新配置之前在配置之后添加小延迟修复了问题,并且至少通过ICAP重新配置至少使用66MHz时钟.Antti LukatsPS我将很快发布下载链接到我的“超级简单”ICAP IP核(它准备好但需要驱动程序) 以上来自于谷歌翻译 以下为原文 Hi IC (i see), ok then I am not the only one ;)I had problem, namly the picoboot.v did not work on spartan3a, when I triggered the reconfig immediatly after config - I assumed that it was related to ICAP clock (what was 66MHz),but then I tested with 50MHz with same failure, the problem was then narrowed to another undocumented feature, namly there must be some "dead time" when s3a is configured but does not accept reconfig from ICAP. This can not be found when reconfig is done by user interaction (as it is for s3a starterkit demos). But a design that immediatly after config starts reconfig will fail, and as picoboot.v only starts config 1 time, so my test setup did not work. Adding small delay after config before reconfig fixed the problem, and at least reconfig via ICAP works with 66MHz clock at least. Antti LukatsPS I will post download link to my "super simple" ICAP IP-core soon (its ready but need driver) |
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AnttiI无法评论Spartan系列中ICAP的速度,但肯定是Virtex-II系列的最高33Mhz。
由于这个约束,我自己不得不限制我的动态部分可重新配置设计.RegardsMH 以上来自于谷歌翻译 以下为原文 Antti I cannot comment the speed of ICAP in Spartan Family, but for sure it is Maximum 33Mhz in Virtex-II series. I myself had to constrain my Dynamic Partially reconfigurable design due to this constraint. RegardsMH |
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据我所知,ICAP是SelectMap(Virtex5,应该等于Spartan3中的Slave Parallel)接口的镜像,除了双向数据总线被分成两个单向总线(不好有内部三态信号)
。适用于Slave Parallell的大部分时间也适用于ICAP。 以上来自于谷歌翻译 以下为原文 ICAP is to my knowledge a mirror of the SelectMap (Virtex5, should be equal to Slave Parallel in Spartan3) interface except that the bi-directional data bus is split into two uni-directional busses (not good to have internal three-state signals). So most timing that applies to Slave Parallell should also apply to the ICAP. |
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虽然是的,但是在一些家庭中,从属并行时钟被指定为高于最大ICAP时钟,因此S3中的正确时序规格数据表仍然会很好有安腾Lukats
以上来自于谷歌翻译 以下为原文 Hi mostly yes, but on some families the slave parallel clock was specified higher then the max ICAP clock, so proper timing spec in S3 a datasheet would still be nice to have Antti Lukats |
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