我终于得到它的工作,我也走过了这个24MHz时钟。主要问题是我正在使用PGX1,但PIM重新路由到PGX2。这是我的配置,如果它可能会帮助某人。/PIC32 MK1024MCF100配置位设置/ /’C源代码配置语句/ /DEVCFG3/使用RID=PraceMac配置,PWMLOCK = OF//PWM IOXCON锁(PWM IOCON寄存器写入访问未被锁定或保护)。N是由端口函数控制的,{ Trac-Matlab配置,PGL1WORE=ON//许可组锁单向配置位(只允许一个重新配置),γ-PrimaMac配置PMDL1WORE = / /外围模块禁用配置(只允许一个重新配置)选择配置(只允许一个重新配置),γ-PracMA配置FUSBIdio1=OU//USB1 USBID选择(USBID引脚由端口函数控制)α-PrimaMac配置FFBUSIO1= OF//USB2 VBUSON选择位(VBUSON PIN由端口函数控制)//DVCFG2α-PrAPMA配置FFLIPDIV= DIVIZ1 / /系统PLL Input Divider(1X分频器),Pracl配置,FPLLRNG=RangeE131326MHz,/系统PLL输入范围(13-26MHz输入)α-PracMA配置FPLILKK=PLLYPOSS//PLL输入时钟选择(POSC被输入到系统PLL)α-PrAPMA配置FPLLMult = Mulr20//PLL乘法器(PLL多载波)y y由20)μPrimaFig=DIVIO4//PLL系统输出时钟分频器(4x除法器)α-PracMA配置VVBROBEN=//VBAT BOR使能(在VBAT模式下启用ZPBOR)α-PrimaMac配置DSBRON=//深度睡眠Bor使能(在深度休眠模式下启用ZPBOR)EEP看门狗Timer Postscaler(1∶2 ^ 36)* PrimaMac配置DSWDTOCS= LPRC//深度睡眠WDT参考时钟选择(选择LPRC作为DSWDT参考时钟)α-PrAPMA配置DSWDTEN = / /深度睡眠看门狗定时器启用(启用深度睡眠模式下的DSWDT)(启用DSCON中的DSEN位),γ-PrimaAg配置BRSEL =高/ /棕色输出电压(BOR跳闸电压2.1V(非OpAMP Dead Curry操作))α-PrimaMaung=OU//USB PLL使能(USB PLL禁用)/DEVCFG1* PrAPMA配置FNOCS= SPLL/ /振荡器选择位(主OSC(HS,EC))GdDMtInV=Wi12127Y128//DMT计数窗口间隔(窗口/间隔值为127/128计数器值)α-PracMA配置FSCOSEN=OF//次级振荡器使能(禁用二级振荡器)α-PrAPMA CONFIG-IESO = ON//内部/外部切换(启用)γ-PracMA配置POSCMOD=EC//主OSCHILCAR配置(外部时钟模式)在OSCO引脚(禁用)上激活的Oraco配置OSCIOFNC=OF//CLKO输出信号,FCKSM=CSEME//时钟切换和监视器选择(启用时钟开关,启用FSCM)α-PrAPMA CONFIG WDTPS=PS1048 57 6/ /看门狗Timer Postscaler(A:PrimaMatlab配置WTTSPGM=Flash编程中的停止/ /看门狗定时器停止(Flash编程中的WDT停止)* PrimaMac配置=正常/ /看门狗定时器窗口模式(看门狗定时器是在非窗口模式下)* PrimaMac配置FFDTEN= OF//看门狗定时器启用(WDT禁用)ONFIG FWDTWSNZ=WiSZZ25//看门狗定时器窗口大小(窗口大小为25%)α-PrAPMA配置DMCTNT=DMT31//死人定时器计数选择(2 ^ 31(2147483648))* PrimaMac配置FDFDN=关闭/ /死人定时器启用(Debug定时器被禁用)//DVCFG0*PracMA配置调试= ON//后台Debugger En可以(调试器被启用)({ TabAGEN)/JTAGEN=OF//JTAG启用(JTAG禁用)一个选择(启动代码和异常代码是MIPS32)α-PrimaMac配置FFAIL= OF//FLASH睡眠模式(当设备处于休眠模式时FLASH被关闭)//软主清除使能(MCLR引脚产生正常系统复位),γ-PracMA配置,sOcGoSc= GAINY2X//次级振荡器增益控制位(2X增益设置)α-PrAPMA COSFIG SCOSBOOST=ON / /次振荡器升压开机启动位(提高振荡器的开机启动)G PascRe= GAIN级ALI/3/主振荡器增益控制位(增益级3(最高))α-PracMA配置POSBOOST=ON//主振荡器Boost启动启动位(提高振荡器的启动启动)α-PrabMA配置EJTAGBEN =正常//EJTAG启动使能(正常EJTAG功能)
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以下为原文
I finally got it working, I also went across this 24Mhz clock.
The main issue is that I was using PGx1 but the PIM reroute it to the PGx2.
Here is the configuration I have in case it might help someone.
// PIC32MK1024MCF100 Configuration Bit Settings
// 'C' source line config statements
// DEVCFG3
// USERID = No Setting
#pragma config PWMLOCK = OFF // PWM IOxCON lock (PWM IOxCON register writes accesses are not locked or protected)
#pragma config FUSBIDIO2 = OFF // USB2 USBID Selection (USBID pin is controlled by the port function)
#pragma config FVBUSIO2 = OFF // USB2 VBUSON Selection bit (VBUSON pin is controlled by the port function)
#pragma config PGL1WAY = ON // Permission Group Lock One Way Configuration bit (Allow only one reconfiguration)
#pragma config PMDL1WAY = ON // Peripheral Module Disable Configuration (Allow only one reconfiguration)
#pragma config IOL1WAY = ON // Peripheral Pin Select Configuration (Allow only one reconfiguration)
#pragma config FUSBIDIO1 = OFF // USB1 USBID Selection (USBID pin is controlled by the port function)
#pragma config FVBUSIO1 = OFF // USB2 VBUSON Selection bit (VBUSON pin is controlled by the port function)
// DEVCFG2
#pragma config FPLLIDIV = DIV_1 // System PLL Input Divider (1x Divider)
#pragma config FPLLRNG = RANGE_13_26_MHZ// System PLL Input Range (13-26 MHz Input)
#pragma config FPLLICLK = PLL_POSC // System PLL Input Clock Selection (POSC is input to the System PLL)
#pragma config FPLLMULT = MUL_20 // System PLL Multiplier (PLL Multiply by 20)
#pragma config FPLLODIV = DIV_4 // System PLL Output Clock Divider (4x Divider)
#pragma config VBATBOREN = ON // VBAT BOR Enable (Enable ZPBOR during VBAT Mode)
#pragma config DSBOREN = ON // Deep Sleep BOR Enable (Enable ZPBOR during Deep Sleep Mode)
#pragma config DSWDTPS = DSPS32 // Deep Sleep Watchdog Timer Postscaler (1:2^36)
#pragma config DSWDTOSC = LPRC // Deep Sleep WDT Reference Clock Selection (Select LPRC as DSWDT Reference clock)
#pragma config DSWDTEN = ON // Deep Sleep Watchdog Timer Enable (Enable DSWDT during Deep Sleep Mode)
#pragma config FDSEN = ON // Deep Sleep Enable (Enable DSEN bit in DSCON)
#pragma config BORSEL = HIGH // Brown-out trip voltage (BOR trip voltage 2.1v (Non-OPAMP deviced operation))
#pragma config UPLLEN = OFF // USB PLL Enable (USB PLL Disabled)
// DEVCFG1
#pragma config FNOSC = SPLL // Oscillator Selection Bits (Primary Osc (HS,EC))
#pragma config DMTINTV = WIN_127_128 // DMT Count Window Interval (Window/Interval value is 127/128 counter value)
#pragma config FSOSCEN = OFF // Secondary Oscillator Enable (Disable Secondary Oscillator)
#pragma config IESO = ON // Internal/External Switch Over (Enabled)
#pragma config POSCMOD = EC // Primary Oscillator Configuration (External clock mode)
#pragma config OSCIOFNC = OFF // CLKO Output Signal Active on the OSCO Pin (Disabled)
#pragma config FCKSM = CSECME // Clock Switching and Monitor Selection (Clock Switch Enabled, FSCM Enabled)
#pragma config WDTPS = PS1048576 // Watchdog Timer Postscaler (1:1048576)
#pragma config WDTSPGM = STOP // Watchdog Timer Stop During Flash Programming (WDT stops during Flash programming)
#pragma config WINDIS = NORMAL // Watchdog Timer Window Mode (Watchdog Timer is in non-Window mode)
#pragma config FWDTEN = OFF // Watchdog Timer Enable (WDT Disabled)
#pragma config FWDTWINSZ = WINSZ_25 // Watchdog Timer Window Size (Window size is 25%)
#pragma config DMTCNT = DMT31 // Deadman Timer Count Selection (2^31 (2147483648))
#pragma config FDMTEN = OFF // Deadman Timer Enable (Deadman Timer is disabled)
// DEVCFG0
#pragma config DEBUG = ON // Background Debugger Enable (Debugger is enabled)
#pragma config JTAGEN = OFF // JTAG Enable (JTAG Disabled)
#pragma config ICESEL = ICS_PGx2 // ICE/ICD Comm Channel Select (Communicate on PGEC1/PGED1)
#pragma config TRCEN = ON // Trace Enable (Trace features in the CPU are enabled)
#pragma config BOOTISA = MIPS32 // Boot ISA Selection (Boot code and Exception code is MIPS32)
#pragma config FSLEEP = OFF // Flash Sleep Mode (Flash is powered down when the device is in Sleep mode)
#pragma config DBGPER = PG_ALL // Debug Mode CPU Access Permission (Allow CPU access to all permission regions)
#pragma config SMCLR = MCLR_NORM // Soft Master Clear Enable (MCLR pin generates a normal system Reset)
#pragma config SOSCGAIN = GAIN_2X // Secondary Oscillator Gain Control bits (2x gain setting)
#pragma config SOSCBOOST = ON // Secondary Oscillator Boost Kick Start Enable bit (Boost the kick start of the oscillator)
#pragma config POSCGAIN = GAIN_LEVEL_3 // Primary Oscillator Gain Control bits (Gain Level 3 (highest))
#pragma config POSCBOOST = ON // Primary Oscillator Boost Kick Start Enable bit (Boost the kick start of the oscillator)
#pragma config EJTAGBEN = NORMAL // EJTAG Boot Enable (Normal EJTAG functionality)