[问答]

Boot Loader和Boot Code的内存选项如何最大限度的利用

问答对人有帮助，内容完整，我也想知道答案 0 我最近有一个工程师问如何最大限度地利用可用的内存空间启动微处理器。我转述了这个问题，并提供了以下答复，我在这里发表评论。对“好实践”的引用也有一定的道理。复述问题： Q1：引导代码可以跨多个骰子扩展为单个包吗？ Q2：引导加载程序和内核可以驻留在不同的设备中吗？初始反应：回答Q1：是的-但是，引导代码应该尽可能小——只用于在启动内核之前启动包括内存在内的和外部设备的基本安全和通信功能。回答Q2：是的。 S34 ML08G201BHI0000 HTTP://wwwyCysP.COM/FIL/20744/Sead是一个很好的内存选择。这部分有两个骰子。对于大多数操作，单独的模具是透明的。然而，有一个独特的特征。Flash设备有一个约束，即当Flash的一部分被写入时，Flash不能被读取。写的时间比读的长很多，所以这会导致额外的等待。有两个芯片，一个芯片可以被读取，而另一个被写入。CyPress在第6节中描述了这个特性，读取了数据表的增强状态。将引导代码保持在最低限度会减轻许多潜在的问题。U-BooT应符合128KB（参考U-BooD设计原则@ HTTPS://www.DNX.DE/WIKI/U-BOOT/DealTrand）。如果需要更多的存储器并且需要物理上连续的存储器，则可以配置多个闪存设备作为单个连续存储设备。这可以通过微处理器外部的逻辑或串行存储器，通过菊花链接存储器来完成。塞浦路斯有多种类型的存储器兼容NXP处理器。有Excel表匹配处理器与推荐存储器@ HTTP://wwwyCypCy.COM/CHIPSET-合作伙伴考虑到特定的处理器正在使用和内存的数量，我可以推荐几个与CyPress的闪存路线图@ HTTP://wwwyCysP.CAM/Studio/RoopMAS/CyPress闪存-路线图对齐的特定选项。我对NXP的I.MX处理器没有洞察力。这可能有助于对ESC的NXP IMX领先者Anna Jamieson提出关于内存推荐的相同问题。注意：如果选择串行存储器来保存启动代码，选择具有复位输入的存储器将确保在通电复位和重新启动之后存储器在特定地址开始。一些旧的串行闪存设备没有重置输入。旧的设备可以通过技术来识别零件号。旧技术使用更大的特征尺寸，例如110纳米或90纳米。参考社区后HTPSP//Cultuy.CyPress 以上来自于百度翻译以下为原文 I recently had an engineer ask how to maximize the available memory space required to start a microprocessor. I paraphrased the question and provided the following response, which I'm posting here for comments. References to "Good practice" with some justification would also be appreciated. Rephrased Question: Q1: Can boot code extend across multiple die is a single package? Q2: Can the bootloader and the kernel reside in different devices? Initial Response: Answer to Q1: Yes – however, the boot code should be as small as possible – used only to initiate basic security and communication functions to internal and external devices including memory before starting the kernel. Answer to Q2: Yes. S34ML08G201BHI000 @ http://www.cypress.com/file/207446/download is a good memory selection. This part does have two die. For most operations, the separate die are transparent. However, there is one unique feature. Flash devices have a constraint that the flash can’t be read while a section of the flash is being written. Writes take much longer than reads, so this can cause extra waits. With two die, one die can be read while the other is being written. Cypress describes this feature in section 6, Read Status Enhanced of the data sheet. Keeping the Boot Code to a minimum will mitigate many of the potential issues. U-Boot should fit in under 128KB (Reference U-Boot Design Principles @ https://www.denx.de/wiki/U-Boot/DesignPrinciples ). If more memory is desired and physically contiguous memory is desired, Multiple Flash devices can be configured to appear as a single contiguous memory device. This can be done with logic outside the microprocessor or with serial memory, by daisy-chaining the memory. Cypress has multiple types of memories compatible with NXP processors. There are Excel tables matching the processors with recommended memories @ http://www.cypress.com/chipset-partners Given the specific processor being used and the amount of memory desired, I can recommend a couple specific options aligned with Cypress’ flash memory roadmap @ http://www.cypress.com/product-r ... lash-memory-roadmap I don’t have the insight into NXP’s i.MX processors. It may help to pose the same question about memory recommendations to the ESC’s NXP IMX lead, Anna Jamieson. Note: If Serial Memory is selected to hold boot code, selecting memory with a reset input will ensure the memory starts at a specific address after both power on reset and re-start. Some of the older serial flash devices don’t have a reset input. Older devices can be identified in the part number by the Technology. Older technologies used larger feature sizes such as 110 nm or 90 nm. Reference Community Post https://community.cypress.com/docs/DOC-10179 0
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答案对人有帮助，有参考价值 0 你好，感谢您发布关于从多芯片堆栈封装闪存设备启动的意见。在处理多个芯片堆叠设备时，您需要注意的一件事是读取模具边界。如果设备是并行NOR或NAND设备，则通常不存在任何问题，因为读取操作是每页。如果多芯片堆叠设备是SPI设备，则它可能不支持跨越芯片边界的突发读取。在这种情况下，如果引导加载程序软件驻留在一个以上的设备中，则主机控制器将需要知道模具边界并相应地执行读取操作。这意味着第一突发读可以从地址0第一模边做，然后第二突发读是必要的从第二死，等等。赛普拉斯SPI设备支持新一代的突发读过死的边界在MCPs。用户可以检查等功能的具体数据表。最好的问候，智以上来自于百度翻译以下为原文 Hi, Thanks for posting your comments about booting from a multiple-die-stack package flash device. One thing you need to pay attention to when dealing with multiple-die-stack devices, is that reading across the die boundary. If the device is Parallel NOR or NAND device, it usually does not have any problem, because the reading operation is per page. If the multiple-die-stack device is a SPI device, it may not support burst read across the die boundary. In that case, if the boot loader software resides in more than one device, the host controller will need to be aware of the die boundary and perform the read operations accordingly. That means the first burst read can be done from Address 0 to the first die boundary, then a second burst read is necessary starting from the 2nd die, so on and so forth. New generation of Cypress SPI devices support burst read across the die boundary in MCPs. Users can check with the specific datasheet for such function. Best regards, Zhi

2018-9-14 15:36:51 评论举报李志刚