请问28035如何提高PWM分辨率

28035芯片，总共要用到8个PWM端口输出，当PWM��率设置为20KHz时，TBPRD设置为1500，那么实际可调占空比的数值范围为0-1500，如何在频率不变的情况下，提高占空比数值范围？
Eric:
使用高精度PWM。
C:ticontrolSUITEdevice_supportf2803xv130DSP2803x_examples_ccsv5hrpwm
C:ticontrolSUITEdevice_supportf2803xv130DSP2803x_examples_ccsv5hrpwm_duty_sfo_v6
                                                                         - ERIC

谢谢你回复， 请问8个通道都可以设置为高分辨率吗？  我安装的是CCS6.1没有找到例子文件夹，能否发个程序样例看看

已经学会使用，非常感谢

分享一下吧   这个硬件是有限制的     有个最高分辨率

按照例程的做法，分辨率只能比原来提高1倍，不知道有没有更好的方法实现更高的分辨率
// Some useful Period vs Frequency values
// SYSCLKOUT = 60 MHz
// ---------------------------
// Period Frequency
// 1000 60 kHz
// 800 75 kHz
// 600 100 kHz
// 500 120 kHz
// 250 240 kHz
// 200 300 kHz
// 100 600 kHz
// 50 1.2 Mhz
// 25 2.4 Mhz
// 20 3.0 Mhz
// 12 5.0 MHz
// 10 6.0 MHz
// 9 6.7 MHz
// 8 7.5 MHz
// 7 8.6 MHz
// 6 10.0 MHz
// 5 12.0 MHz


void HRPWM1_Config(Uint16 period)
[
// ePWM1 register configuration with HRPWM
// ePWM1A toggle low/high with MEP control on Rising edge
EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
EPwm1Regs.TBPRD = period-1; // PWM frequency = 1 / period
EPwm1Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially
EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension
EPwm1Regs.CMPB = period / 2; // set duty 50% initially
EPwm1Regs.TBPHS.all = 0;
EPwm1Regs.TBCTR = 0;
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // EPwm1 is the Master
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // PWM toggle low/high
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.CBU = AQ_SET;
EALLOW;
EPwm1Regs.HRCNFG.all = 0x0;
EPwm1Regs.HRCNFG.bit.EDGMODE = HR_REP; //MEP control on Rising edge
EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP;
EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
EDIS;
]