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Hi，
all. 问题如下： 在调试完接收AGC功能后，我进行接收的中射频信号质量测试。 使用信号源仪器灌入调制信号进行测试。 测试的思路大致如下： 1. 信号源仪器发出基带调制信号，如QPSK 、pi/4 DQPSK、 16QAM、64QAM； 2. AD9361在较好的接收强度下（-30dBm上下）接收； 3. FPGA直接实时绘制接收的IQ图，以此来查看（AD9361出来为零中频复信号）。 但是在实际测试中，有如下几个疑惑点可能会对测试造成影响： 1. 信号源仪器和板子时钟源差异，这点我已通过使用外部仪器的时钟源输入到AD9361解决； 2. 信号源发出的信号一般会经过成型滤波（根升余弦、升余弦、高斯），所以一般要求接收基带需要对应的匹配滤波。但是这点上，我是想直接去查看IQ图，也就是不经过匹配滤波（那样可能需求针对去增加代码）。另外，如果发射rectangle方式，这种经过实际的中射频链路，是会有信号失真。所以也不好用来评估IQ图。 然后 我进行了接收通道测试： 1. AD9361配置： 状态机方式： FDD； 时钟源： 外部10MHz（仪器输出） 发射频点： 2.4GHz； 接收频点： 1GHz； 中频滤波： LTE 5MHz模板 （信号带宽4.5MHz） 接收增益： Slow Attack AGC方式 AGC设置如下： 2. 测试方案： 1. E4438C作为信号源 ，产生对应的调制信号，仪器发射频点对应子板接收频点2.3GHz； 2. 测试调制信号（单载波）： 2.1. 4QAM 、 16 QAM 、 pi/4 DQPSK; 2.2. 成型滤波器： 根升余弦（0.35）、升余弦（0.35）、高斯（0.5），矩形窗 2.3. 符号速率： 500KSPS 、 1MSPS。 3. 评估方法： 因为AD9361接收输出的为零中频正交两路信号，因此直接抓取IQ信号，通过FPGA内嵌逻辑分析仪（chipscope）查看IQ轨迹图。 4. 测试结果（这里展示16QAM，rectangle成型的测试结果） 1. 本人测试结果-- 在zedboard板子上测试 图1. 16QAM接收轨迹图， 符号速率500KSPS，矩形窗(Rectangle)成型发射 2. 朋友测试——（某公司使用AD9361自己做的板子测试） 其他说明： 测试之前，我已经完成芯片的数字接口测试，即在基带芯片发射随机数据，通过AD9361的loopback功能（寄存器0x3F5=0x01），接收数据是一致的。 另外，基带设计上面，接收IQ数据通道的时钟采用AD9361随路过来的时钟，所以数据接口方面应该没有问题。即参考如下方式进行： 我的轨迹图上的符号点还是显得较发散，正常来说这个点应该相对收敛集中的。 我和朋友的板子是有差异（他是他们公司自己做的硬件板子），其他方面，我是采用LTE 5M模板（AD936x Wireless Transceiver Evaluation工具里面直接有）。 
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5个回答
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你那些图好像看不到，能否在发一下
建议你还是用板子上的晶体做参考时钟，范围19-50MHz，只要PLL能够锁定就可以 正常通过chipscope抓到的数据是可以看到时域信号的，在bus plot里面 如果可以的话把你的寄存器配置脚本一并发上来看下，谢谢 |
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miweurwer 发表于 2018-8-20 08:03 Ok。 我改为附件上传。 一： 我在zedboard上测试结果： 朋友在其制作的硬件板子上测试结果： 二： 为了实验室测试需求，仪器和板子我使用同一个时钟源，所以只好使用10MHz，使用板子自带的晶振，测试会发现轨迹图在旋转（因为收发频偏造成，调整DCXO也不太好使）。 三： 1.我使用的配置文件如下， 如果可以请帮我在您手头可用的板子上帮忙测试。其基带信号的特性如之前描述。 配置脚本（LTE 5M ，FDD ，Slow AGC，Tx 2.5GHz，Rx 2.4GHz，晶振采用板子自身40MHz）： //************************************************************ // AD9361 R2 Auto Generated Initialization Script: This script was // generated using the AD9361 Customer software Version 2.1.3 //************************************************************ // Profile: LTE 5 MHz // REFCLK_IN: 40.000 MHz RESET_FPGA RESET_DUT BlockWrite 2,6 // Set ADI FPGA SPI to 20Mhz SPIWrite 3DF,01 // Required for proper operation ReadPartNumber SPIWrite 2A6,0E // Enable Master Bias SPIWrite 2A8,0E // Set Bandgap Trim REFCLK_Scale 40.000000,1,2 // Sets local variables in script engine, user can ignore SPIWrite 292,08 // Set DCXO Coarse Tune[5:0]. Coarse and Fine nominal values used with eval system. Other nominal values may be needed in a customer system SPIWrite 293,80 // Set DCXO Fine Tune [12:5] SPIWrite 294,00 // Set DCXO Fine Tune [4:0] SPIWrite 2AB,07 // Set RF PLL reflclk scale to REFCLK * 2 SPIWrite 2AC,FF // Set RF PLL reflclk scale to REFCLK * 2 SPIWrite 009,07 // Enable Clocks WAIT 20 // waits 20 ms //************************************************************ // Set BBPLL Frequency: 983.040000 //************************************************************ SPIWrite 045,00 // Set BBPLL reflclk scale to REFCLK /1 SPIWrite 046,03 // Set BBPLL Loop Filter Charge Pump current SPIWrite 048,E8 // Set BBPLL Loop Filter C1, R1 SPIWrite 049,5B // Set BBPLL Loop Filter R2, C2, C1 SPIWrite 04A,35 // Set BBPLL Loop Filter C3,R2 SPIWrite 04B,E0 // Allow calibration to occur and set cal count to 1024 for max accuracy SPIWrite 04E,10 // Set calibration clock to REFCLK/4 for more accuracy SPIWrite 043,29 // BBPLL Freq Word (Fractional[7:0]) SPIWrite 042,5C // BBPLL Freq Word (Fractional[15:8]) SPIWrite 041,12 // BBPLL Freq Word (Fractional[23:16]) SPIWrite 044,18 // BBPLL Freq Word (Integer[7:0]) SPIWrite 03F,05 // Start BBPLL Calibration SPIWrite 03F,01 // Clear BBPLL start calibration bit SPIWrite 04C,86 // Increase BBPLL KV and phase margin SPIWrite 04D,01 // Increase BBPLL KV and phase margin SPIWrite 04D,05 // Increase BBPLL KV and phase margin WAIT_CALDONE BBPLL,2000 // Wait for BBPLL to lock, Timeout 2sec, Max BBPLL VCO Cal Time: 345.600 us (Done when 0x05E[7]==1) SPIRead 05E // Check BBPLL locked status (0x05E[7]==1 is locked) SPIWrite 002,5E // Setup Tx Digital Filters/ Channels SPIWrite 003,5E // Setup Rx Digital Filters/ Channels SPIWrite 004,03 // Select Rx input pin(A,B,C)/ Tx out pin (A,B) SPIWrite 00A,03 // Set BBPLL post divide rate //************************************************************ // Program Tx FIR: C:Program Files (x86)Analog DevicesAD9361R2 // Evaluation Software 2.1.3DigitalFiltersLTE5_MHz.ftr //************************************************************ SPIWrite 065,FA // Enable clock to Tx FIR Filter and set Filter gain Setting SPIWrite 060,00 // Write FIR coefficient address SPIWrite 061,FB // Write FIR coefficient data[7:0] SPIWrite 062,FF // Write FIR coefficient data[15:8] SPIWrite 065,FE // Set Write EN to push data into FIR filter register map SPIWrite 064,00 // Write to Read only register to delay ~1us SPIWrite 064,00 // Write to Read only register to delay ~1us SPIWrite 060,01 SPIWrite 061,00 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,02 SPIWrite 061,05 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,03 SPIWrite 061,17 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,04 SPIWrite 061,24 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,05 SPIWrite 061,27 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,06 SPIWrite 061,12 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,07 SPIWrite 061,F2 SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,08 SPIWrite 061,DC SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,09 SPIWrite 061,E6 SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,0A SPIWrite 061,0B SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,0B SPIWrite 061,30 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,0C SPIWrite 061,2D SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,0D SPIWrite 061,FE SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,0E SPIWrite 061,C5 SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,0F SPIWrite 061,B9 SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,10 SPIWrite 061,F1 SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,11 SPIWrite 061,45 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,12 SPIWrite 061,67 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,13 SPIWrite 061,2A SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,14 SPIWrite 061,B6 SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,15 SPIWrite 061,74 SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,16 SPIWrite 061,AF SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,17 SPIWrite 061,47 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,18 SPIWrite 061,B6 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,19 SPIWrite 061,85 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,1A SPIWrite 061,C7 SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,1B SPIWrite 061,1E SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,1C SPIWrite 061,36 SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,1D SPIWrite 061,1B SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,1E SPIWrite 061,0E SPIWrite 062,01 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,1F SPIWrite 061,1F SPIWrite 062,01 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,20 SPIWrite 061,17 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,21 SPIWrite 061,CB SPIWrite 062,FE SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,22 SPIWrite 061,7A SPIWrite 062,FE SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,23 SPIWrite 061,9E SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,24 SPIWrite 061,54 SPIWrite 062,01 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,25 SPIWrite 061,01 SPIWrite 062,02 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,26 SPIWrite 061,CE SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,27 SPIWrite 061,9D SPIWrite 062,FE SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,28 SPIWrite 061,70 SPIWrite 062,FD SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,29 SPIWrite 061,9E SPIWrite 062,FE SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,2A SPIWrite 061,5D SPIWrite 062,01 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,2B SPIWrite 061,35 SPIWrite 062,03 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,2C SPIWrite 061,2C SPIWrite 062,02 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,2D SPIWrite 061,CB SPIWrite 062,FE SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,2E SPIWrite 061,0A SPIWrite 062,FC SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,2F SPIWrite 061,C3 SPIWrite 062,FC SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,30 SPIWrite 061,DB SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,31 SPIWrite 061,DA SPIWrite 062,04 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,32 SPIWrite 061,BA SPIWrite 062,04 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,33 SPIWrite 061,CC SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,34 SPIWrite 061,08 SPIWrite 062,FA SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,35 SPIWrite 061,13 SPIWrite 062,F9 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,36 SPIWrite 061,03 SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,37 SPIWrite 061,86 SPIWrite 062,07 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,38 SPIWrite 061,91 SPIWrite 062,0A SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,39 SPIWrite 061,50 SPIWrite 062,03 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,3A SPIWrite 061,BC SPIWrite 062,F5 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,3B SPIWrite 061,A6 SPIWrite 062,ED SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,3C SPIWrite 061,B0 SPIWrite 062,F6 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,3D SPIWrite 061,C8 SPIWrite 062,12 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,3E SPIWrite 061,96 SPIWrite 062,36 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,3F SPIWrite 061,7D SPIWrite 062,4F SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,40 SPIWrite 061,7D SPIWrite 062,4F SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,41 SPIWrite 061,96 SPIWrite 062,36 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,42 SPIWrite 061,C8 SPIWrite 062,12 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,43 SPIWrite 061,B0 SPIWrite 062,F6 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,44 SPIWrite 061,A6 SPIWrite 062,ED SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,45 SPIWrite 061,BC SPIWrite 062,F5 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,46 SPIWrite 061,50 SPIWrite 062,03 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,47 SPIWrite 061,91 SPIWrite 062,0A SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,48 SPIWrite 061,86 SPIWrite 062,07 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,49 SPIWrite 061,03 SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,4A SPIWrite 061,13 SPIWrite 062,F9 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,4B SPIWrite 061,08 SPIWrite 062,FA SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,4C SPIWrite 061,CC SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,4D SPIWrite 061,BA SPIWrite 062,04 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,4E SPIWrite 061,DA SPIWrite 062,04 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,4F SPIWrite 061,DB SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,50 SPIWrite 061,C3 SPIWrite 062,FC SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,51 SPIWrite 061,0A SPIWrite 062,FC SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,52 SPIWrite 061,CB SPIWrite 062,FE SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,53 SPIWrite 061,2C SPIWrite 062,02 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,54 SPIWrite 061,35 SPIWrite 062,03 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,55 SPIWrite 061,5D SPIWrite 062,01 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,56 SPIWrite 061,9E SPIWrite 062,FE SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,57 SPIWrite 061,70 SPIWrite 062,FD SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,58 SPIWrite 061,9D SPIWrite 062,FE SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,59 SPIWrite 061,CE SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,5A SPIWrite 061,01 SPIWrite 062,02 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,5B SPIWrite 061,54 SPIWrite 062,01 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,5C SPIWrite 061,9E SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,5D SPIWrite 061,7A SPIWrite 062,FE SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,5E SPIWrite 061,CB SPIWrite 062,FE SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,5F SPIWrite 061,17 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,60 SPIWrite 061,1F SPIWrite 062,01 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,61 SPIWrite 061,0E SPIWrite 062,01 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,62 SPIWrite 061,1B SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,63 SPIWrite 061,36 SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,64 SPIWrite 061,1E SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,65 SPIWrite 061,C7 SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,66 SPIWrite 061,85 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,67 SPIWrite 061,B6 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,68 SPIWrite 061,47 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,69 SPIWrite 061,AF SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,6A SPIWrite 061,74 SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,6B SPIWrite 061,B6 SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,6C SPIWrite 061,2A SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,6D SPIWrite 061,67 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,6E SPIWrite 061,45 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,6F SPIWrite 061,F1 SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,70 SPIWrite 061,B9 SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,71 SPIWrite 061,C5 SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,72 SPIWrite 061,FE SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,73 SPIWrite 061,2D SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,74 SPIWrite 061,30 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,75 SPIWrite 061,0B SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,76 SPIWrite 061,E6 SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,77 SPIWrite 061,DC SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,78 SPIWrite 061,F2 SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,79 SPIWrite 061,12 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,7A SPIWrite 061,27 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,7B SPIWrite 061,24 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,7C SPIWrite 061,17 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,7D SPIWrite 061,05 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,7E SPIWrite 061,00 SPIWrite 062,00 SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 060,7F SPIWrite 061,FB SPIWrite 062,FF SPIWrite 065,FE SPIWrite 064,00 SPIWrite 064,00 SPIWrite 065,F8 // Disable clock to Tx Filter //************************************************************ // Program Rx FIR: C:Program Files (x86)Analog DevicesAD9361R2 // Evaluation Software 2.1.3DigitalFiltersLTE5_MHz.ftr //************************************************************ SPIWrite 0F5,FA // Enable clock to Rx FIR Filter SPIWrite 0F6,02 // Write Filter Gain setting SPIWrite 0F0,00 // Write FIR coefficient address SPIWrite 0F1,F6 // Write FIR coefficient data[7:0] SPIWrite 0F2,FF // Write FIR coefficient data[15:8] SPIWrite 0F5,FE // Set Write EN to push data into FIR filter register map SPIWrite 0F4,00 // Dummy Write to Read only register to delay ~1us SPIWrite 0F4,00 // Dummy Write to Read only register to delay ~1us SPIWrite 0F0,01 SPIWrite 0F1,EA SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,02 SPIWrite 0F1,EC SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,03 SPIWrite 0F1,EB SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,04 SPIWrite 0F1,0B SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,05 SPIWrite 0F1,14 SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,06 SPIWrite 0F1,1C SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,07 SPIWrite 0F1,FB SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,08 SPIWrite 0F1,E2 SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,09 SPIWrite 0F1,D6 SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,0A SPIWrite 0F1,FA SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,0B SPIWrite 0F1,27 SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,0C SPIWrite 0F1,3E SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,0D SPIWrite 0F1,17 SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,0E SPIWrite 0F1,D2 SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,0F SPIWrite 0F1,A8 SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,10 SPIWrite 0F1,D0 SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,11 SPIWrite 0F1,31 SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,12 SPIWrite 0F1,77 SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,13 SPIWrite 0F1,53 SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,14 SPIWrite 0F1,D4 SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,15 SPIWrite 0F1,66 SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,16 SPIWrite 0F1,7E SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,17 SPIWrite 0F1,1E SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,18 SPIWrite 0F1,C0 SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,19 SPIWrite 0F1,BF SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,1A SPIWrite 0F1,FD SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,1B SPIWrite 0F1,1A SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,1C SPIWrite 0F1,F5 SPIWrite 0F2,FE SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,1D SPIWrite 0F1,D6 SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,1E SPIWrite 0F1,09 SPIWrite 0F2,01 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,1F SPIWrite 0F1,67 SPIWrite 0F2,01 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,20 SPIWrite 0F1,6D SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,21 SPIWrite 0F1,DA SPIWrite 0F2,FE SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,22 SPIWrite 0F1,2B SPIWrite 0F2,FE SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,23 SPIWrite 0F1,35 SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,24 SPIWrite 0F1,37 SPIWrite 0F2,01 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,25 SPIWrite 0F1,55 SPIWrite 0F2,02 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,26 SPIWrite 0F1,4C SPIWrite 0F2,01 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,27 SPIWrite 0F1,CB SPIWrite 0F2,FE SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,28 SPIWrite 0F1,17 SPIWrite 0F2,FD SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,29 SPIWrite 0F1,07 SPIWrite 0F2,FE SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,2A SPIWrite 0F1,1A SPIWrite 0F2,01 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,2B SPIWrite 0F1,93 SPIWrite 0F2,03 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,2C SPIWrite 0F1,DE SPIWrite 0F2,02 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,2D SPIWrite 0F1,29 SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,2E SPIWrite 0F1,AA SPIWrite 0F2,FB SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,2F SPIWrite 0F1,ED SPIWrite 0F2,FB SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,30 SPIWrite 0F1,5A SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,31 SPIWrite 0F1,3C SPIWrite 0F2,05 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,32 SPIWrite 0F1,BD SPIWrite 0F2,05 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,33 SPIWrite 0F1,81 SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,34 SPIWrite 0F1,AB SPIWrite 0F2,F9 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,35 SPIWrite 0F1,D4 SPIWrite 0F2,F7 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,36 SPIWrite 0F1,FE SPIWrite 0F2,FD SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,37 SPIWrite 0F1,CE SPIWrite 0F2,07 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,38 SPIWrite 0F1,22 SPIWrite 0F2,0C SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,39 SPIWrite 0F1,DE SPIWrite 0F2,04 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,3A SPIWrite 0F1,B4 SPIWrite 0F2,F5 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,3B SPIWrite 0F1,99 SPIWrite 0F2,EB SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,3C SPIWrite 0F1,F0 SPIWrite 0F2,F3 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,3D SPIWrite 0F1,89 SPIWrite 0F2,11 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,3E SPIWrite 0F1,3C SPIWrite 0F2,38 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,3F SPIWrite 0F1,6A SPIWrite 0F2,53 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,40 SPIWrite 0F1,6A SPIWrite 0F2,53 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,41 SPIWrite 0F1,3C SPIWrite 0F2,38 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,42 SPIWrite 0F1,89 SPIWrite 0F2,11 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,43 SPIWrite 0F1,F0 SPIWrite 0F2,F3 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,44 SPIWrite 0F1,99 SPIWrite 0F2,EB SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,45 SPIWrite 0F1,B4 SPIWrite 0F2,F5 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,46 SPIWrite 0F1,DE SPIWrite 0F2,04 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,47 SPIWrite 0F1,22 SPIWrite 0F2,0C SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,48 SPIWrite 0F1,CE SPIWrite 0F2,07 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,49 SPIWrite 0F1,FE SPIWrite 0F2,FD SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,4A SPIWrite 0F1,D4 SPIWrite 0F2,F7 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,4B SPIWrite 0F1,AB SPIWrite 0F2,F9 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,4C SPIWrite 0F1,81 SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,4D SPIWrite 0F1,BD SPIWrite 0F2,05 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,4E SPIWrite 0F1,3C SPIWrite 0F2,05 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,4F SPIWrite 0F1,5A SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,50 SPIWrite 0F1,ED SPIWrite 0F2,FB SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,51 SPIWrite 0F1,AA SPIWrite 0F2,FB SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,52 SPIWrite 0F1,29 SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,53 SPIWrite 0F1,DE SPIWrite 0F2,02 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,54 SPIWrite 0F1,93 SPIWrite 0F2,03 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,55 SPIWrite 0F1,1A SPIWrite 0F2,01 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,56 SPIWrite 0F1,07 SPIWrite 0F2,FE SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,57 SPIWrite 0F1,17 SPIWrite 0F2,FD SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,58 SPIWrite 0F1,CB SPIWrite 0F2,FE SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,59 SPIWrite 0F1,4C SPIWrite 0F2,01 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,5A SPIWrite 0F1,55 SPIWrite 0F2,02 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,5B SPIWrite 0F1,37 SPIWrite 0F2,01 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,5C SPIWrite 0F1,35 SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,5D SPIWrite 0F1,2B SPIWrite 0F2,FE SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,5E SPIWrite 0F1,DA SPIWrite 0F2,FE SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,5F SPIWrite 0F1,6D SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,60 SPIWrite 0F1,67 SPIWrite 0F2,01 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,61 SPIWrite 0F1,09 SPIWrite 0F2,01 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,62 SPIWrite 0F1,D6 SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,63 SPIWrite 0F1,F5 SPIWrite 0F2,FE SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,64 SPIWrite 0F1,1A SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,65 SPIWrite 0F1,FD SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,66 SPIWrite 0F1,BF SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,67 SPIWrite 0F1,C0 SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,68 SPIWrite 0F1,1E SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,69 SPIWrite 0F1,7E SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,6A SPIWrite 0F1,66 SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,6B SPIWrite 0F1,D4 SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,6C SPIWrite 0F1,53 SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,6D SPIWrite 0F1,77 SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,6E SPIWrite 0F1,31 SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,6F SPIWrite 0F1,D0 SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,70 SPIWrite 0F1,A8 SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,71 SPIWrite 0F1,D2 SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,72 SPIWrite 0F1,17 SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,73 SPIWrite 0F1,3E SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,74 SPIWrite 0F1,27 SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,75 SPIWrite 0F1,FA SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,76 SPIWrite 0F1,D6 SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,77 SPIWrite 0F1,E2 SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,78 SPIWrite 0F1,FB SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,79 SPIWrite 0F1,1C SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,7A SPIWrite 0F1,14 SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,7B SPIWrite 0F1,0B SPIWrite 0F2,00 SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,7C SPIWrite 0F1,EB SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,7D SPIWrite 0F1,EC SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,7E SPIWrite 0F1,EA SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F0,7F SPIWrite 0F1,F6 SPIWrite 0F2,FF SPIWrite 0F5,FE SPIWrite 0F4,00 SPIWrite 0F4,00 SPIWrite 0F5,F8 // Disable clock to Rx Filter //************************************************************ // Setup the Parallel Port (Digital Data Interface) //************************************************************ SPIWrite 010,C8 // I/O Config. Tx Swap IQ; Rx Swap IQ; Tx CH Swap, Rx CH Swap; Rx Frame Mode; 2R2T bit; Invert data bus; Invert DATA_CLK SPIWrite 011,00 // I/O Config. Alt Word Order; -Rx1; -Rx2; -Tx1; -Tx2; Invert Rx Frame; Delay Rx Data SPIWrite 012,10 // I/O Config. Rx=2*Tx; Swap Ports; SDR; LVDS; Half Duplex; Single Port; Full Port; Swap Bits SPIWrite 006,0F // PPORT Rx Delay (adjusts Tco Dataclk->Data) SPIWrite 007,F0 // PPORT TX Delay (adjusts setup/hold FBCLK->Data) SPIWrite 03C,22 // CLK_OUT slew; LVDS: Rx Term; Bypass Bias R; Tx LO VCM; Bias[2:0] SPIWrite 03D,00 // LVDS polarity invert SPIWrite 03E,00 // LVDS polarity invert //************************************************************ // Setup AuxDAC //************************************************************ SPIWrite 018,00 // AuxDAC1 Word[9:2] SPIWrite 019,00 // AuxDAC2 Word[9:2] SPIWrite 01A,00 // AuxDAC1 Config and Word[1:0] SPIWrite 01B,00 // AuxDAC2 Config and Word[1:0] SPIWrite 023,FF // AuxDAC Manaul/Auto Control SPIWrite 026,00 // AuxDAC Manual Select Bit/GPO Manual Select SPIWrite 030,00 // AuxDAC1 Rx Delay SPIWrite 031,00 // AuxDAC1 Tx Delay SPIWrite 032,00 // AuxDAC2 Rx Delay SPIWrite 033,00 // AuxDAC2 Tx Delay //************************************************************ // Setup AuxADC //************************************************************ SPIWrite 00B,00 // Temp Sensor Setup (Offset) SPIWrite 00C,00 // Temp Sensor Setup (Temp Window) SPIWrite 00D,03 // Temp Sensor Setup (Periodic Measure) SPIWrite 00F,04 // Temp Sensor Setup (Decimation) SPIWrite 01C,10 // AuxADC Setup (Clock Div) SPIWrite 01D,01 // AuxADC Setup (Decimation/Enable) //************************************************************ // Setup Control Outs //************************************************************ SPIWrite 035,0B // Ctrl Out index SPIWrite 036,0F // Ctrl Out [7:0] output enable //************************************************************ // Setup GPO //************************************************************ SPIWrite 03A,27 // Set number of REFCLK cycles for 1us delay timer SPIWrite 020,00 // GPO Auto Enable Setup in RX and TX SPIWrite 027,03 // GPO Manual and GPO auto value in ALERT SPIWrite 028,00 // GPO_0 RX Delay SPIWrite 029,00 // GPO_1 RX Delay SPIWrite 02A,00 // GPO_2 RX Delay SPIWrite 02B,00 // GPO_3 RX Delay SPIWrite 02C,00 // GPO_0 TX Delay SPIWrite 02D,00 // GPO_1 TX Delay SPIWrite 02E,00 // GPO_2 TX Delay SPIWrite 02F,00 // GPO_3 TX Delay //************************************************************ // Setup RF PLL non-frequency-dependent registers //************************************************************ SPIWrite 261,00 // Set Rx LO Power mode SPIWrite 2A1,00 // Set Tx LO Power mode SPIWrite 248,0B // Enable Rx VCO LDO SPIWrite 288,0B // Enable Tx VCO LDO SPIWrite 246,02 // Set VCO Power down TCF bits SPIWrite 286,02 // Set VCO Power down TCF bits SPIWrite 249,8E // Set VCO cal length SPIWrite 289,8E // Set VCO cal length SPIWrite 23B,80 // Enable Rx VCO cal SPIWrite 27B,80 // Enable Tx VCO cal SPIWrite 243,0D // Set Rx prescaler bias SPIWrite 283,0D // Set Tx prescaler bias SPIWrite 23D,00 // Clear Half VCO cal clock setting SPIWrite 27D,00 // Clear Half VCO cal clock setting SPIWrite 015,0C // Set Dual Synth mode bit SPIWrite 014,1D // Set Force ALERT State bit SPIWrite 013,01 // Set ENSM FDD mode WAIT 1 // waits 1 ms SPIWrite 23D,04 // Start RX CP cal WAIT_CALDONE RXCP,100 // Wait for CP cal to complete, Max RXCP Cal time: 460.800 (us)(Done when 0x244[7]==1) SPIWrite 27D,04 // Start TX CP cal WAIT_CALDONE TXCP,100 // Wait for CP cal to complete, Max TXCP Cal time: 460.800 (us)(Done when 0x284[7]==1) SPIWrite 23D,00 // Disable RX CP Calibration since the CP Cal start bit is not self-clearing. Only important if the script is run again without restting the DUT SPIWrite 27D,00 // Disable TX CP Calibration since the CP Cal start bit is not self-clearing. Only important if the script is run again without restting the DUT //************************************************************ // FDD RX,TX Synth Frequency: 2400.000000,2500.000000 MHz //************************************************************ //************************************************************ // Setup Rx Frequency-Dependent Syntheisizer Registers //************************************************************ SPIWrite 23A,4A // Set VCO Output level[3:0] SPIWrite 239,C0 // Set Init ALC Value[3:0] and VCO Varactor[3:0] SPIWrite 242,0D // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] SPIWrite 238,68 // Set VCO Cal Offset[3:0] SPIWrite 245,00 // Set VCO Cal Ref Tcf[2:0] SPIWrite 251,09 // Set VCO Varactor Reference[3:0] SPIWrite 250,70 // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] SPIWrite 23B,91 // Set Synth Loop Filter charge pump current (Icp) SPIWrite 23E,D4 // Set Synth Loop Filter C2 and C1 SPIWrite 23F,DF // Set Synth Loop Filter R1 and C3 SPIWrite 240,09 // Set Synth Loop Filter R3 //************************************************************ // Setup Tx Frequency-Dependent Syntheisizer Registers //************************************************************ SPIWrite 27A,4A // Set VCO Output level[3:0] SPIWrite 279,C0 // Set Init ALC Value[3:0] and VCO Varactor[3:0] SPIWrite 282,0D // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] SPIWrite 278,70 // Set VCO Cal Offset[3:0] SPIWrite 285,00 // Set VCO Cal Ref Tcf[2:0] SPIWrite 291,09 // Set VCO Varactor Reference[3:0] SPIWrite 290,70 // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] SPIWrite 27B,8F // Set Synth Loop Filter charge pump current (Icp) SPIWrite 27E,D4 // Set Synth Loop Filter C2 and C1 SPIWrite 27F,DF // Set Synth Loop Filter R1 and C3 SPIWrite 280,09 // Set Synth Loop Filter R3 //************************************************************ // Write Rx and Tx Frequency Words //************************************************************ SPIWrite 233,00 // Write Rx Synth Fractional Freq Word[7:0] SPIWrite 234,00 // Write Rx Synth Fractional Freq Word[15:8] SPIWrite 235,00 // Write Rx Synth Fractional Freq Word[22:16] SPIWrite 232,00 // Write Rx Synth Integer Freq Word[10:8] SPIWrite 231,78 // Write Rx Synth Integer Freq Word[7:0] SPIWrite 005,11 // Set LO divider setting SPIWrite 273,00 // Write Tx Synth Fractional Freq Word[7:0] SPIWrite 274,00 // Write Tx Synth Fractional Freq Word[15:8] SPIWrite 275,00 // Write Tx Synth Fractional Freq Word[22:16] SPIWrite 272,00 // Write Tx Synth Integer Freq Word[10:8] SPIWrite 271,7D // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal) SPIWrite 005,11 // Set LO divider setting SPIRead 247 // Check RX RF PLL lock status (0x247[1]==1 is locked) SPIRead 287 // Check TX RF PLL lock status (0x287[1]==1 is locked) //************************************************************ // Program Mixer GM Sub-table //************************************************************ SPIWrite 13F,02 // Start Clock SPIWrite 138,0F // Addr Table Index SPIWrite 139,78 // Gain SPIWrite 13A,00 // Bias SPIWrite 13B,00 // GM SPIWrite 13F,06 // Write Words SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) SPIWrite 13C,00 // Delay ~1us (Dummy Write) SPIWrite 138,0E // Addr Table Index SPIWrite 139,74 // Gain SPIWrite 13A,00 // Bias SPIWrite 13B,0D // GM SPIWrite 13F,06 // Write Words SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) SPIWrite 13C,00 // Delay ~1us (Dummy Write) SPIWrite 138,0D // Addr Table Index SPIWrite 139,70 // Gain SPIWrite 13A,00 // Bias SPIWrite 13B,15 // GM SPIWrite 13F,06 // Write Words SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) SPIWrite 13C,00 // Delay ~1us (Dummy Write) SPIWrite 138,0C // Addr Table Index SPIWrite 139,6C // Gain SPIWrite 13A,00 // Bias SPIWrite 13B,1B // GM SPIWrite 13F,06 // Write Words SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) SPIWrite 13C,00 // Delay ~1us (Dummy Write) SPIWrite 138,0B // Addr Table Index SPIWrite 139,68 // Gain SPIWrite 13A,00 // Bias SPIWrite 13B,21 // GM SPIWrite 13F,06 // Write Words SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) SPIWrite 13C,00 // Delay ~1us (Dummy Write) SPIWrite 138,0A // Addr Table Index SPIWrite 139,64 // Gain SPIWrite 13A,00 // Bias SPIWrite 13B,25 // GM SPIWrite 13F,06 // Write Words SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) SPIWrite 13C,00 // Delay ~1us (Dummy Write) SPIWrite 138,09 // Addr Table Index SPIWrite 139,60 // Gain SPIWrite 13A,00 // Bias SPIWrite 13B,29 // GM SPIWrite 13F,06 // Write Words SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) SPIWrite 13C,00 // Delay ~1us (Dummy Write) SPIWrite 138,08 // Addr Table Index SPIWrite 139,5C // Gain SPIWrite 13A,00 // Bias SPIWrite 13B,2C // GM SPIWrite 13F,06 // Write Words SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) SPIWrite 13C,00 // Delay ~1us (Dummy Write) SPIWrite 138,07 // Addr Table Index SPIWrite 139,58 // Gain SPIWrite 13A,00 // Bias SPIWrite 13B,2F // GM SPIWrite 13F,06 // Write Words SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) SPIWrite 13C,00 // Delay ~1us (Dummy Write) SPIWrite 138,06 // Addr Table Index SPIWrite 139,54 // Gain SPIWrite 13A,00 // Bias SPIWrite 13B,31 // GM SPIWrite 13F,06 // Write Words SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) SPIWrite 13C,00 // Delay ~1us (Dummy Write) SPIWrite 138,05 // Addr Table Index SPIWrite 139,50 // Gain SPIWrite 13A,00 // Bias SPIWrite 13B,33 // GM SPIWrite 13F,06 // Write Words SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) SPIWrite 13C,00 // Delay ~1us (Dummy Write) SPIWrite 138,04 // Addr Table Index SPIWrite 139,4C // Gain SPIWrite 13A,00 // Bias SPIWrite 13B,34 // GM SPIWrite 13F,06 // Write Words SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) SPIWrite 13C,00 // Delay ~1us (Dummy Write) SPIWrite 138,03 // Addr Table Index SPIWrite 139,48 // Gain SPIWrite 13A,00 // Bias SPIWrite 13B,35 // GM SPIWrite 13F,06 // Write Words SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) SPIWrite 13C,00 // Delay ~1us (Dummy Write) SPIWrite 138,02 // Addr Table Index SPIWrite 139,30 // Gain SPIWrite 13A,00 // Bias SPIWrite 13B,3A // GM SPIWrite 13F,06 // Write Words SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) SPIWrite 13C,00 // Delay ~1us (Dummy Write) SPIWrite 138,01 // Addr Table Index SPIWrite 139,18 // Gain SPIWrite 13A,00 // Bias SPIWrite 13B,3D // GM SPIWrite 13F,06 // Write Words SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) SPIWrite 13C,00 // Delay ~1us (Dummy Write) SPIWrite 138,00 // Addr Table Index SPIWrite 139,00 // Gain SPIWrite 13A,00 // Bias SPIWrite 13B,3E // GM SPIWrite 13F,06 // Write Words SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) SPIWrite 13C,00 // Delay ~1us (Dummy Write) SPIWrite 13F,02 // Clear Write Bit SPIWrite 13C,00 // Delay for 3 ADCCLK/16 clock cycles (Dummy Write) SPIWrite 13C,00 // Delay ~1us (Dummy Write) SPIWrite 13F,00 // Stop Clock //************************************************************ // Program Rx Gain Tables with GainTable2300MHz.csv //************************************************************ SPIWrite 137,1A // Start Gain Table Clock SPIWrite 130,00 // Gain Table Index SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,00 // TIA & LPF Word SPIWrite 133,20 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,01 // Gain Table Index SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,00 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,02 // Gain Table Index SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,00 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,03 // Gain Table Index SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,01 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,04 // Gain Table Index SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,02 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,05 // Gain Table Index SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,03 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,06 // Gain Table Index SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,04 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,07 // Gain Table Index SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,05 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,08 // Gain Table Index SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,03 // TIA & LPF Word SPIWrite 133,20 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,09 // Gain Table Index SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,04 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,0A // Gain Table Index SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,05 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,0B // Gain Table Index SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,06 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,0C // Gain Table Index SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,07 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,0D // Gain Table Index SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,08 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,0E // Gain Table Index SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,09 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,0F // Gain Table Index SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,0A // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,10 // Gain Table Index SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,0B // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,11 // Gain Table Index SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,0C // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,12 // Gain Table Index SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,0D // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,13 // Gain Table Index SPIWrite 131,01 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,0E // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,14 // Gain Table Index SPIWrite 131,02 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,09 // TIA & LPF Word SPIWrite 133,20 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,15 // Gain Table Index SPIWrite 131,02 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,0A // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,16 // Gain Table Index SPIWrite 131,02 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,0B // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,17 // Gain Table Index SPIWrite 131,02 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,0C // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,18 // Gain Table Index SPIWrite 131,02 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,0D // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,19 // Gain Table Index SPIWrite 131,02 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,0E // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,1A // Gain Table Index SPIWrite 131,02 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,0F // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,1B // Gain Table Index SPIWrite 131,02 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,10 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,1C // Gain Table Index SPIWrite 131,02 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,2B // TIA & LPF Word SPIWrite 133,20 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,1D // Gain Table Index SPIWrite 131,02 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,2C // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,1E // Gain Table Index SPIWrite 131,04 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,27 // TIA & LPF Word SPIWrite 133,20 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,1F // Gain Table Index SPIWrite 131,04 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,28 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,20 // Gain Table Index SPIWrite 131,04 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,29 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,21 // Gain Table Index SPIWrite 131,04 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,2A // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,22 // Gain Table Index SPIWrite 131,04 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,2B // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,23 // Gain Table Index SPIWrite 131,24 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,21 // TIA & LPF Word SPIWrite 133,20 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,24 // Gain Table Index SPIWrite 131,24 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,22 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,25 // Gain Table Index SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,20 // TIA & LPF Word SPIWrite 133,20 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,26 // Gain Table Index SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,21 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,27 // Gain Table Index SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,22 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,28 // Gain Table Index SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,23 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,29 // Gain Table Index SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,24 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,2A // Gain Table Index SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,25 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,2B // Gain Table Index SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,26 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,2C // Gain Table Index SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,27 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,2D // Gain Table Index SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,28 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,2E // Gain Table Index SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,29 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,2F // Gain Table Index SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,2A // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,30 // Gain Table Index SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,2B // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,31 // Gain Table Index SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,2C // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,32 // Gain Table Index SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,2D // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,33 // Gain Table Index SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,2E // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,34 // Gain Table Index SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,2F // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,35 // Gain Table Index SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,30 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,36 // Gain Table Index SPIWrite 131,44 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,31 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,37 // Gain Table Index SPIWrite 131,64 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,2E // TIA & LPF Word SPIWrite 133,20 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,38 // Gain Table Index SPIWrite 131,64 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,2F // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,39 // Gain Table Index SPIWrite 131,64 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,30 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,3A // Gain Table Index SPIWrite 131,64 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,31 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,3B // Gain Table Index SPIWrite 131,64 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,32 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,3C // Gain Table Index SPIWrite 131,64 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,33 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,3D // Gain Table Index SPIWrite 131,64 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,34 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,3E // Gain Table Index SPIWrite 131,64 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,35 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,3F // Gain Table Index SPIWrite 131,64 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,36 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,40 // Gain Table Index SPIWrite 131,64 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,37 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,41 // Gain Table Index SPIWrite 131,64 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,38 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,42 // Gain Table Index SPIWrite 131,65 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,38 // TIA & LPF Word SPIWrite 133,20 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,43 // Gain Table Index SPIWrite 131,66 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,38 // TIA & LPF Word SPIWrite 133,20 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,44 // Gain Table Index SPIWrite 131,67 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,38 // TIA & LPF Word SPIWrite 133,20 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,45 // Gain Table Index SPIWrite 131,68 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,38 // TIA & LPF Word SPIWrite 133,20 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,46 // Gain Table Index SPIWrite 131,69 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,38 // TIA & LPF Word SPIWrite 133,20 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,47 // Gain Table Index SPIWrite 131,6A // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,38 // TIA & LPF Word SPIWrite 133,20 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,48 // Gain Table Index SPIWrite 131,6B // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,38 // TIA & LPF Word SPIWrite 133,20 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,49 // Gain Table Index SPIWrite 131,6C // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,38 // TIA & LPF Word SPIWrite 133,20 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,4A // Gain Table Index SPIWrite 131,6D // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,38 // TIA & LPF Word SPIWrite 133,20 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,4B // Gain Table Index SPIWrite 131,6E // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,38 // TIA & LPF Word SPIWrite 133,20 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,4C // Gain Table Index SPIWrite 131,6F // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,38 // TIA & LPF Word SPIWrite 133,20 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,4D // Gain Table Index SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,00 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,4E // Gain Table Index SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,00 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,4F // Gain Table Index SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,00 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,50 // Gain Table Index SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,00 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,51 // Gain Table Index SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,00 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,52 // Gain Table Index SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,00 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,53 // Gain Table Index SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,00 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,54 // Gain Table Index SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,00 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,55 // Gain Table Index SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,00 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,56 // Gain Table Index SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,00 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,57 // Gain Table Index SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,00 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,58 // Gain Table Index SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,00 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,59 // Gain Table Index SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,00 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 130,5A // Gain Table Index SPIWrite 131,00 // Ext LNA, Int LNA, & Mixer Gain Word SPIWrite 132,00 // TIA & LPF Word SPIWrite 133,00 // DC Cal bit & Dig Gain Word SPIWrite 137,1E // Write Words SPIWrite 134,00 // Dummy Write to delay 3 ADCCLK/16 cycles SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 137,1A // Clear Write Bit SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 134,00 // Dummy Write to delay ~1us SPIWrite 137,00 // Stop Gain Table Clock //************************************************************ // Setup Rx AGC Slow Attack/Hybrid Registers //************************************************************ SPIWrite 0FA,EA // Gain Control Mode Select SPIWrite 0FB,08 // Full Table/Digital Gain Select SPIWrite 0FC,23 // ADC Overrange Sample Size SPIWrite 0FD,4C // Max Full/LMT Gain Table Index SPIWrite 0FE,44 // Peak Overload Wait Time SPIWrite 100,6F // Max Digital Gain SPIWrite 101,0A // AGC Inner High Threshold SPIWrite 103,08 // Large LMT Step Size SPIWrite 104,2F // ADC Small Overload Threshold SPIWrite 105,3A // ADC Large Overload Threshold SPIWrite 106,22 // ADC Overload Step Sizes SPIWrite 107,31 // Large LMT Overload Threshold SPIWrite 108,39 // Small LMT Overload Threshold SPIWrite 111,4A // Settling Delay SPIWrite 11A,27 // Initial LMT Gain Limit SPIWrite 120,0C // Prevent Inc & AGC Inner Low Thresh SPIWrite 121,44 // LMT Overload Exceeded Counters SPIWrite 122,44 // ADC Overload Exceeded Counters SPIWrite 123,11 // AGC Inner High & Low Step Sizes SPIWrite 124,F5 // Gain Update Counter<7:0> SPIWrite 125,3B // Gain Update Counter<15:8> SPIWrite 128,03 // Digital Sat Exceeded Counter SPIWrite 129,56 // AGC Outer High & Low Thresholds SPIWrite 12A,22 // AGC Outer High & Low Step Sizes //************************************************************ // RX Baseband Filter Tuning (Real BW: 2.250000 MHz) 3dB Filter // Corner @ 3.150000 MHz) //************************************************************ SPIWrite 1FB,02 // RX Freq Corner (MHz) SPIWrite 1FC,20 // RX Freq Corner (Khz) SPIWrite 1F8,23 // Rx BBF Tune Divider[7:0] SPIWrite 1F9,1E // RX BBF Tune Divider[8] SPIWrite 1D5,3F // Set Rx Mix LO CM SPIWrite 1C0,03 // Set GM common mode SPIWrite 1E2,02 // Enable Rx1 Filter Tuner SPIWrite 1E3,02 // Enable Rx2 Filter Tuner SPIWrite 016,80 // Start RX Filter Tune WAIT_CALDONE RXFILTER,2000 // Wait for RX filter to tune, Max Cal Time: 21.718 us (Done when 0x016[7]==0) SPIWrite 1E2,03 // Disable Rx Filter Tuner (Rx1) SPIWrite 1E3,03 // Disable Rx Filter Tuner (Rx2) //************************************************************ // TX Baseband Filter Tuning (Real BW: 2.250000 MHz) 3dB Filter // Corner @ 3.600000 MHz) //************************************************************ SPIWrite 0D6,1F // TX BBF Tune Divider[7:0] SPIWrite 0D7,1E // TX BBF Tune Divider[8] SPIWrite 0CA,22 // Enable Tx Filter Tuner SPIWrite 016,40 // Start Tx Filter Tune WAIT_CALDONE TXFILTER,2000 // Wait for TX filter to tune, Max Cal Time: 11.195 us (Done when 0x016[6]==0) SPIWrite 0CA,26 // Disable Tx Filter Tuner (Both Channels) //************************************************************ // RX TIA Setup: Setup values scale based on RxBBF calibration // results. See information in Calibration Guide. //************************************************************ SPIRead 1EB // Read RXBBF C3(MSB) SPIRead 1EC // Read RXBBF C3(LSB) SPIRead 1E6 // Read RXBBF R2346 SPIWrite 1DB,E0 // Set TIA selcc[2:0] SPIWrite 1DD,18 // Set RX TIA1 C MSB[6:0] SPIWrite 1DF,18 // Set RX TIA2 C MSB[6:0] SPIWrite 1DC,40 // Set RX TIA1 C LSB[5:0] SPIWrite 1DE,40 // Set RX TIA2 C LSB[5:0] //************************************************************ // TX Secondary Filter Calibration Setup: Real Bandwidth // 2.250000MHz, 3dB Corner @ 11.250000MHz //************************************************************ SPIWrite 0D2,3B // TX Secondary Filter PDF Cap cal[5:0] SPIWrite 0D1,04 // TX Secondary Filter PDF Res cal[3:0] SPIWrite 0D0,59 // Pdampbias //************************************************************ // ADC Setup: Tune ADC Performance based on RX analog filter tune // corner. Real Bandwidth: 2.213200 MHz, ADC Clock Frequency: // 122.880000 MHz. The values in registers 0x200 - 0x227 need to be // calculated using the equations in the Calibration Guide. //************************************************************ SPIRead 1EB // Read RxBBF C3 MSB after calibration SPIRead 1EC // Read RxBBF C3 LSB after calibration SPIRead 1E6 // Read RxBBF R3 after calibration SPIWrite 200,00 SPIWrite 201,00 SPIWrite 202,00 SPIWrite 203,24 SPIWrite 204,24 SPIWrite 205,00 SPIWrite 206,00 SPIWrite 207,6D SPIWrite 208,90 SPIWrite 209,34 SPIWrite 20A,42 SPIWrite 20B,5B SPIWrite 20C,45 SPIWrite 20D,59 SPIWrite 20E,00 SPIWrite 20F,70 SPIWrite 210,70 SPIWrite 211,70 SPIWrite 212,40 SPIWrite 213,40 SPIWrite 214,40 SPIWrite 215,43 SPIWrite 216,43 SPIWrite 217,43 SPIWrite 218,2E SPIWrite 219,8C SPIWrite 21A,10 SPIWrite 21B,0E SPIWrite 21C,8C SPIWrite 21D,10 SPIWrite 21E,0E SPIWrite 21F,8C SPIWrite 220,10 SPIWrite 221,1B SPIWrite 222,1C SPIWrite 223,40 SPIWrite 224,40 SPIWrite 225,2C SPIWrite 226,00 SPIWrite 227,00 //************************************************************ // Setup and Run BB DC and RF DC Offset Calibrations //************************************************************ SPIWrite 193,3F SPIWrite 190,0F // Set BBDC tracking shift M value, only applies when BB DC tracking enabled SPIWrite 194,01 // BBDC Cal setting SPIWrite 016,01 // Start BBDC offset cal WAIT_CALDONE BBDC,2000 // BBDC Max Cal Time: 26302.083 us. Cal done when 0x016[0]==0 SPIWrite 185,20 // Set RF DC offset Wait Count SPIWrite 186,32 // Set RF DC Offset Count[7:0] SPIWrite 187,24 // Settings for RF DC cal SPIWrite 18B,83 // Settings for RF DC cal SPIWrite 188,05 // Settings for RF DC cal SPIWrite 189,30 // Settings for RF DC cal SPIWrite 016,02 // Start RFDC offset cal WAIT_CALDONE RFDC,2000 // RFDC Max Cal Time: 357847.656 us //************************************************************ // Tx Quadrature Calibration Settings //************************************************************ SPIRead 0A3 // Masked Read: Read lower 6 bits, overwrite [7:6] below SPIWrite 0A0,15 // Set TxQuadcal NCO frequency SPIWrite 0A3,00 // Set TxQuadcal NCO frequency (Only update bits [7:6]) SPIWrite 0A1,7B // Tx Quad Cal Configuration, Phase and Gain Cal Enable SPIWrite 0A9,FF // Set Tx Quad Cal Count SPIWrite 0A2,7F // Set Tx Quad Cal Kexp SPIWrite 0A5,01 // Set Tx Quad Cal Magnitude Threshhold SPIWrite 0A6,01 // Set Tx Quad Cal Magnitude Threshhold SPIWrite 0AA,25 // Set Tx Quad Cal Gain Table index SPIWrite 0A4,F0 // Set Tx Quad Cal Settle Count SPIWrite 0AE,00 // Set Tx Quad Cal LPF Gain index incase Split table mode used SPIWrite 169,C0 // Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration SPIWrite 016,10 // Start Tx Quad cal WAIT_CALDONE TXQUAD,2000 // Wait for cal to complete (Done when 0x016[4]==0) SPIWrite 16A,75 // Set Kexp Phase SPIWrite 16B,95 // Set Kexp Amplitude & Prevent Positive Gain Bit SPIWrite 169,CF // Enable Rx Quadrature Calibration Tracking SPIWrite 18B,AD // Enable BB and RF DC Tracking Calibrations SPIWrite 012,10 // Cals done, Set PPORT Config SPIWrite 013,01 // Set ENSM FDD/TDD bit SPIWrite 015,0C // Set Dual Synth Mode, FDD External Control bits properly //************************************************************ // Set Tx Attenuation: Tx1: 10.00 dB, Tx2: 10.00 dB //************************************************************ SPIWrite 073,28 SPIWrite 074,00 SPIWrite 075,28 SPIWrite 076,00 //************************************************************ // Setup RSSI and Power Measurement Duration Registers //************************************************************ SPIWrite 150,0E // RSSI Measurement Duration 0, 1 SPIWrite 151,00 // RSSI Measurement Duration 2, 3 SPIWrite 152,FF // RSSI Weighted Multiplier 0 SPIWrite 153,00 // RSSI Weighted Multiplier 1 SPIWrite 154,00 // RSSI Weighted Multiplier 2 SPIWrite 155,00 // RSSI Weighted Multiplier 3 SPIWrite 156,00 // RSSI Delay SPIWrite 157,00 // RSSI Wait SPIWrite 158,0D // RSSI Mode Select SPIWrite 15C,67 // Power Measurement Duration |
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我问下你这个输入的信号是LTE的5MHz载波信号吗？如果不是你用这个文件可能会导致采样率有问题。
如果是LTE的信号，那星座图应该的正的，不应该是斜的方向。 另外LTE信号对于同步要求非常严格的（如果是LTE信号确实需要把仪器的10M提供给板子做参考并且最好测试FDD模式的） 另外你可能还要确认下AGC是否已经锁定了 ，通过查看2B0寄存器的值可以看到增益应该是没有变化的 |
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miweurwer 发表于 2018-8-20 08:23 Hi， 1.灌入信号不是LTE 5MHz的载波信号，而是一个基带16QAM调制，符号速率500KSPS，rectangle成型信号； 2. 关于轨迹图（纠正下，这个是轨迹图，不是星座图）方向，这个是一个随机初相位，是由仪器发出的信号和板子芯片接收的一个固定随机相位偏差，一般看到的星座图是会经过解调，也就是一些相位频偏估计然后信道估计得出。 我这个测试并没有那些，只是直接将零中频IQ信号画出来，是一种轨迹图（类似FSK一维调制可以直接看时域眼图）； 3. 我已经对板子和仪器做了时钟源同步，带来的好处就是消除载波偏差，轨迹图不会旋转； 4. AGC是已经正常工作（这个已经在单载波输入信号测试接收动态范围）了的，读取2B0是可以保持恒定。 我现在读取一些其他寄存器发现有些问题，0x169,0x170~0x182. 我发现读取的0x170寄存器在不断变化，这个寄存器是接收正交校准的保存值。 |
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建议将对比数据源和AD9361采集的数据。第一张图看起来比较正常，存在的相位差使图有点歪斜，很轻微的调幅噪声；第二张图，建议先看看信号源 。
0x170~0x182是直流失调/正交误差的一个实时校正，影响不大。 |
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只有小组成员才能发言，加入小组>>
987 浏览 2 评论
给ADUM4223 增加信号驱动15V电压就不正常， 波动很大会被烧是什么情况？
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1937 浏览 1 评论
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4268 浏览 2 评论
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1520浏览 3评论
AD7190状态寄存器一直是0x80，连续转换模式下RDY不拉低
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给ADUM4223 增加信号驱动15V电压就不正常， 波动很大会被烧是什么情况？
1384浏览 2评论
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