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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENtiTY TAX2 IS GENERIC(R1:INTEGER:=3;R2:INTEGER:=4;R3:INTEGER:=5;R4:INTEGER:=6); PORT(CLK,K4,K5:IN STD_LOGIC; S0,S1:IN STD_LOGIC_VECTOR(3 DOWNTO 0); W:IN STD_LOGIC_VECTOR(4 DOWNTO 0); Y3,Y2,Y1,Y0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END; ARCHITECTURE ONE OF TAX2 IS SIGNAL LC,DD_RATE,LC_RATE,RATE,BAI,SHI,GE,POINT:INTEGER:=0; SIGNAL FLAG:STD_LOGIC; BEGIN FLAG<='1' WHEN K4='1' ELSE '0'; LC<=10*CONV_INTEGER(S1)+CONV_INTEGER(S0); LC_RATE<=INTEGER(10+R1*3+R2*(LC-6)) WHEN LC>6 AND FLAG='1' AND K5='0' ELSE INTEGER(10+R1*(LC-3)) WHEN LC>3 AND FLAG='1' AND K5='0' ELSE 10 WHEN FLAG='1' AND K5='0' ELSE INTEGER(15+R3*3+R4*(LC-6)) WHEN LC>6 AND FLAG='1' AND K5='1' ELSE INTEGER(15+R3*(LC-3)) WHEN LC>3 AND FLAG='1' AND K5='1' ELSE 15 WHEN FLAG='1' AND K5='1' ELSE 0; DD_RATE<=INTEGER(R1*CONV_INTEGER(W)) WHEN FLAG='1' AND K5='0' ELSE INTEGER(R3*CONV_INTEGER(W)) WHEN FLAG='1' AND K5='1' ELSE 0; RATE<=LC_RATE+DD_RATE; BAI<=INTEGER(RATE) / 100; SHI<=INTEGER(RATE-100*BAI) / 10; GE<=INTEGER(RATE-100*BAI-10*SHI) / 1; POINT<=INTEGER(RATE-100*BAI-10*SHI-1*GE); Y0<=CONV_STD_LOGIC_VECTOR(POINT,4); Y1<=CONV_STD_LOGIC_VECTOR(GE,4); Y2<=CONV_STD_LOGIC_VECTOR(SHI,4); Y3<=CONV_STD_LOGIC_VECTOR(BAI,4) WHEN BAI/=0 ELSE "1111"; END; |
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