关于用verilog语言编写检测开关的问题

如果现在一共有18个拨动开关，用什么样的办法检测被关闭的两个开关是哪？只要求测出最左和最右两端的开关。我自己的思路部分代码如下：
input[17:0] rang;
wire[17:0] rang_1;

assign rang_1 ={rang[0], rang[1], rang[2],rang[3],rang[4],rang[5],rang[6],rang[7], rang[8],rang[9], rang[10],rang[11],rang[12],rang[13],rang[14],rang[15],rang[16],rang[17]};



always @(posedge clk or negedge clr_n)

if(!clr_n)

left_temp <=5'd0;

else

casex(rang)

18'b1xxxxxxxxxxxxxxxxx:left_temp <= 5'd1;

18'b01xxxxxxxxxxxxxxxx:left_temp <= 5'd2;

18'b001xxxxxxxxxxxxxxx:left_temp <= 5'd3;

18'b0001xxxxxxxxxxxxxx:left_temp <= 5'd4;

18'b00001xxxxxxxxxxxxx:left_temp <= 5'd5;

18'b000001xxxxxxxxxxxx:left_temp <= 5'd6;

18'b0000001xxxxxxxxxxx:left_temp <= 5'd7;

18'b00000001xxxxxxxxxx:left_temp <= 5'd8;

18'b000000001xxxxxxxxx:left_temp <= 5'd9;

18'b0000000001xxxxxxxx:left_temp <= 5'd10;

18'b00000000001xxxxxxx:left_temp <= 5'd11;

18'b000000000001xxxxxx:left_temp <= 5'd12;

18'b0000000000001xxxxx:left_temp <= 5'd13;

18'b00000000000001xxxx:left_temp <= 5'd14;

18'b000000000000001xxx:left_temp <= 5'd15;

18'b0000000000000001xx:left_temp <= 5'd16;

18'b00000000000000001x:left_temp <= 5'd17;

18'b000000000000000001:left_temp <= 5'd18;

default: left_temp <= 5'd0;

endcase



always @(posedge clk or negedge clr_n)

if(!clr_n)

right_temp <=5'd13;

else

casex(rang)

18'bxxxxxxxxxxxxxxxxx1:right_temp <= 5'd18;

18'bxxxxxxxxxxxxxxxx10:right_temp <= 5'd17;

18'bxxxxxxxxxxxxxxx100:right_temp <= 5'd16;

18'bxxxxxxxxxxxxxx1000:right_temp <= 5'd15;

18'bxxxxxxxxxxxxx10000:right_temp <= 5'd14;

18'bxxxxxxxxxxxx100000:right_temp <= 5'd13;

18'bxxxxxxxxxxx1000000:right_temp <= 5'd12;

18'bxxxxxxxxxx10000000:right_temp <= 5'd11;

18'bxxxxxxxxx100000000:right_temp <= 5'd10;

18'bxxxxxxxx1000000000:right_temp <= 5'd9;

18'bxxxxxxx10000000000:right_temp <= 5'd8;

18'bxxxxxx100000000000:right_temp <= 5'd7;

18'bxxxxx1000000000000:right_temp <= 5'd6;

18'bxxxx10000000000000:right_temp <= 5'd5;

18'bxxx100000000000000:right_temp <= 5'd4;

18'bxx1000000000000000:right_temp <= 5'd3;

18'bx10000000000000000:right_temp <= 5'd2;

18'b100000000000000000:right_temp <= 5'd1;

default: right_temp <= 5'd19;

endcase