如何在原理图源中连接ISE上的7段显示器

这是有道理的。
我只是不确定如何在原理图中连接时钟。
否则我很确定我正确连接了输入



以下为原文

This makes sense. I'm just not sure how to wire in the clock in the schematic. Otherwise I'm pretty sure I wired the inputs properly

我不需要在设计的其余部分使用时钟。
我的困惑只是我不知道这个时钟连接到7段显示器的位置。
我将输入分别连接到数字的每个段（CA，CB，CC等）我不知道如何将时钟实现到此，以便我可以使显示工作



以下为原文

I don't need a clock in the rest of the design. my confusion is just im not sure where this clock connects to the 7 segment display. I wired the inputs to each segment of a digit separately (CA,CB,CC, etc.) Im not sure how to implement the clock into this so that i can get the displays working

嗯......我认为你需要开始数字逻辑设计课程。
在这样的课程中，您将学习门，寄存器，锁存器，时钟，存储器，状态机，顺序逻辑等。
大多数课程（如果不是全部）将要求使用硬件描述语言（VHDL或Verilog）而不是原理图进行设计输入。
学习基础知识。
通过结构化课程计划，您将学习更好，更快，而不是关于如何执行此操作或如何执行此操作的散点图问题。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
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我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Hmmm...  I think you need to take a course in beginning digital logic design.  In such a course you will learn about gates, registers, latches, clocks, memories, state machines, sequenced logic, etc.
 
Most courses (if not all) will require design entry in a hardware description language, either VHDL or Verilog, rather than schematics.  Learn the basics.  You will learn better and faster with a structured course plan than with scatter-shot questions about how to do this or how to do that.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

嘿，
我正在使用带有原理图的Xilinx ISE Webpack，并希望设计一个七段显示器，但我没有找到构建块。
我使用Digilent Basys2作为FPGA。
我可以用逻辑块设计简单的东西，比如和/或但是在板上开始这个。
但在符号中我找不到S-S-D的人。
我可以按照图片上显示的方式做些什么吗？



以下为原文

Hey,
 
I am using the Xilinx ISE Webpack with schematic and want to design a seven segment display but I didn't find a building block. I use Digilent Basys2 as FPGA. I can design simple things with logical block like and/or but and start this on the board. But nowhere in the symbols I can find someone for the S-S-D. Can I do something like in the way shown on the pictures?
 
 

sebastick写道：
嘿，
我正在使用带有原理图的Xilinx ISE Webpack，并希望设计一个七段显示器，但我没有找到构建块。
我使用Digilent Basys2作为FPGA。
我可以用逻辑块设计简单的东西，比如和/或但是在板上开始这个。
但在符号中我找不到S-S-D的人。
我可以按照图片上显示的方式做些什么吗？
当然，7段显示器没有任何“构建块”。
这是一个简单的设计，但它还取决于显示器的类型（共阳极，共阴极）以及它们如何连线。
----------------------------是的，我这样做是为了谋生。



以下为原文

sebastick wrote:
Hey,
 
I am using the Xilinx ISE Webpack with schematic and want to design a seven segment display but I didn't find a building block. I use Digilent Basys2 as FPGA. I can design simple things with logical block like and/or but and start this on the board. But nowhere in the symbols I can find someone for the S-S-D. Can I do something like in the way shown on the pictures?

Of course there aren't any "building blocks" for a 7-segment display. It's a trivial design, but it also depends on the type of display (common anode, common cathode) and how it's all wired up.
----------------------------Yes, I do this for a living.

应避免FPGA逻辑设计的原理图捕获。
您应该学习Verilog或VHDL来实现FPGA逻辑。
关于七段显示逻辑的构建块，您是否花时间查看该帖子中＃2帖子中的链接页面？
在学习新的想法和实践时，示例或参考设计是最好的学习工具。
链接页面提供了示例实现，供您根据自己的目的和想象进行复制和自定义。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Schematic capture for FPGA logic design should be avoided.  You should be learning either Verilog or VHDL for implementing FPGA logic.
 
In regards to building blocks for seven segment display logic, did you take the time to review the linked pages in post #2 in this thread?
 
When learning new ideas and practices, example or reference designs are among the best learning tools.  The linked pages offer example implementations for you to copy and customise to your purposes and your imagination.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

我的问题是我不知道如何解决这个问题。
我有I / O标记，多路复用器等。但实际上我不知道如何用一个按钮构建所有块来计算7段显示。
如果我按下一个按钮7SD应该计数，我想要的功能？
有什么建议么？



以下为原文

My problem is that I don't know how to figure it out.
I have I/O marker, multiplexer etc. But I actually dont't know how to build all the blocks to count the 7-segment display with a single button. I would like the function if I push a button the 7SD should count up? 
Any suggestions?