VDMA到STREAM自定义IP但LED没有闪烁

当我尝试这个代码数据不断，但不正确的数据。
模块qwerty＃（//用户在这里添加参数//用户参数结束//不要修改超出此行的参数// AXI4Stream sink：数据宽度参数整数C_S_AXIS_TDATA_WIDTH = 8）（//用户在这里添加端口//用户
端口//不要修改此行以外的端口// AXI4Stream接收器：时钟输入线S_AXIS_ACLK，// AXI4Stream接收器：复位输入线S_AXIS_ARESETN，//准备接受输出线S_AXIS_TREADY中的数据，输出reg [7：0]
S_led，//输入线中的数据[C_S_AXIS_TDATA_WIDTH-1：0] S_AXIS_TDATA，//字节限定符//输入线[（C_S_AXIS_TDATA_WIDTH / 8）-1：0] S_AXIS_TSTRB，//表示最后一个数据包输入线S_AXIS_TLAST的边界，/
/数据在有效输入线S_AXIS_TVALID）;
//函数调用clogb2，它返回一个整数，该整数具有日志基数的上限值//函数整数clogb2（输入整数bit_depth）;
begin for（clogb2 = 0; bit_depth> 0; clogb2 = clogb2 + 1）bit_depth = bit_depth >> 1;
end endfunction //输入数据总数。
localparam NUMBER_OF_INPUT_WORDS = 8;
// bit_num给出了解决FIFO的“NUMBER_OF_INPUT_WORDS”大小所需的最小位数。
localparam bit_num = clogb2（NUMBER_OF_INPUT_WORDS-1）;
//定义状态机的状态//控制状态机监视输入流数据到FIFO的写入，//从FIFO参数[1：0]输出流数据IDLE = 1'b0，//这个
是初始/空闲状态WRITE_FIFO = 1'b1;
//在这种状态下，FIFO用//输入流数据S_AXIS_TDATA写入wire axis_tready;
//状态变量reg mst_exec_state;
// FIFO实现信号genvar byte_index;
// FIFO写使能线fifo_wren;
// FIFO full flag reg fifo_full_flag;
// FIFO写指针reg [bit_num-1：0] write_pointer;
// sink已接受所有流数据并存储在FIFO reg write_done中;
// I / O连接分配分配S_AXIS_TREADY = axis_tready;
//控制状态机实现始终@（posedge S_AXIS_ACLK）如果（！S_AXIS_ARESETN）//同步复位（低电平有效）开始mst_exec_state结束其他情况（mst_exec_state）IDLE：//当//有tvalid时，接收器开始接受tdata
标记//有效流数据的存在如果（S_AXIS_TVALID）开始mst_exec_state结束，则开始mst_exec_state结束WRITE_FIFO：//当接收器接受了所有流输入数据时，//接口将功能切换到流主控器if（writes_done）
开始mst_exec_state结束其他开始//接收器接受并将tdata //存储到FIFO mst_exec_state end endcase end // AXI Streaming Sink // //示例设计接收器总是准备好接受S_AXIS_TDATA，直到// FIFO未填充
NUMBER_OF_INPUT_WORDS个输入字数。
赋值axis_tready =（（mst_exec_state == WRITE_FIFO）＆amp;＆amp;（write_pointer always @（posedge S_AXIS_ACLK）begin if（！S_AXIS_ARESETN）begin write_pointer writes_done end else if（write_pointer begin if if（fifo_wren）begin // write pointer在每次之后递增
当FIFO写信号被使能时写入FIFO // write_pointer writes_done end if（（write_pointer == NUM​​BER_OF_INPUT_WORDS-1）|| S_AXIS_TLAST）开始//当NUMBER_OF_INPUT_WORDS个数据流数据//已写入FIFO时，reads_done被置位

其中也标有S_AXIS_TLAST（保留用于可选用法）.write_done end end end // FIFO写使能生成assign fifo_wren = S_AXIS_TVALID＆amp;＆amp;＆amp; axis_tready; // FIFO实现生成（byte_index = 0; byte_index 以下为原文

when im trying in this code data is coming continously ,,but not correct data.
module qwerty #
    (
        // Users to add parameters here

        // User parameters ends
        // Do not modify the parameters beyond this line

        // AXI4Stream sink: Data Width
        parameter integer C_S_AXIS_TDATA_WIDTH    = 8
    )
    (
        // Users to add ports here

        // User ports ends
        // Do not modify the ports beyond this line

        // AXI4Stream sink: Clock
        input wire  S_AXIS_ACLK,
        // AXI4Stream sink: Reset
        input wire  S_AXIS_ARESETN,
        // Ready to accept data in
        output wire  S_AXIS_TREADY,
        output  reg [7:0] S_led,
        // Data in
        input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA,
        // Byte qualifier
        //input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB,
        // Indicates boundary of last packet
        input wire  S_AXIS_TLAST,
        // Data is in valid
        input wire  S_AXIS_TVALID
    );
    // function called clogb2 that returns an integer which has the
    // value of the ceiling of the log base 2.
    function integer clogb2 (input integer bit_depth);
      begin
        for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
          bit_depth = bit_depth >> 1;
      end
    endfunction

    // Total number of input data.
    localparam NUMBER_OF_INPUT_WORDS  = 8;
    // bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO.
    localparam bit_num  = clogb2(NUMBER_OF_INPUT_WORDS-1);
    // Define the states of state machine
    // The control state machine oversees the writing of input streaming data to the FIFO,
    // and outputs the streaming data from the FIFO
    parameter [1:0] IDLE = 1'b0,        // This is the initial/idle state

                    WRITE_FIFO  = 1'b1; // In this state FIFO is written with the
                                        // input stream data S_AXIS_TDATA
    wire      axis_tready;
    // State variable
    reg mst_exec_state;  
    // FIFO implementation signals
    genvar byte_index;     
    // FIFO write enable
    wire fifo_wren;
    // FIFO full flag
    reg fifo_full_flag;
    // FIFO write pointer
    reg [bit_num-1:0] write_pointer;
    // sink has accepted all the streaming data and stored in FIFO
      reg writes_done;
    // I/O Connections assignments

    assign S_AXIS_TREADY    = axis_tready;
    // Control state machine implementation
    always @(posedge S_AXIS_ACLK)
    begin  
      if (!S_AXIS_ARESETN)
      // Synchronous reset (active low)
        begin
          mst_exec_state <= IDLE;
        end  
      else
        case (mst_exec_state)
          IDLE:
            // The sink starts accepting tdata when
            // there tvalid is asserted to mark the
            // presence of valid streaming data
              if (S_AXIS_TVALID)
                begin
                  mst_exec_state <= WRITE_FIFO;
                end
              else
                begin
                  mst_exec_state <= IDLE;
                end
          WRITE_FIFO:
            // When the sink has accepted all the streaming input data,
            // the interface swiches functionality to a streaming master
            if (writes_done)
              begin
                mst_exec_state <= IDLE;
              end
            else
              begin
                // The sink accepts and stores tdata
                // into FIFO
                mst_exec_state <= WRITE_FIFO;
              end

        endcase
    end
    // AXI Streaming Sink
    //
    // The example design sink is always ready to accept the S_AXIS_TDATA  until
    // the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words.
    assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1));

    always@(posedge S_AXIS_ACLK)
    begin
      if(!S_AXIS_ARESETN)
        begin
          write_pointer <= 0;
          writes_done <= 1'b0;
        end  
      else
        if (write_pointer <= NUMBER_OF_INPUT_WORDS-1)
          begin
            if (fifo_wren)
              begin
                // write pointer is incremented after every write to the FIFO
                // when FIFO write signal is enabled.
                write_pointer <= write_pointer + 1;
                writes_done <= 1'b0;
              end
              if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST)
                begin
                  // reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data
                  // has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage).
                  writes_done <= 1'b1;
                end
          end  
    end

    // FIFO write enable generation
    assign fifo_wren = S_AXIS_TVALID && axis_tready;

    // FIFO Implementation
    generate
      for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1)
      begin:FIFO_GEN

        reg  [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1];

        // Streaming input data is stored in FIFO

        always @( posedge S_AXIS_ACLK )
                begin
                  if (fifo_wren) //&& S_AXIS_TSTRB[byte_index])
                    begin
                      stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8];
                                 S_led <= stream_data_fifo[1];
                                 S_led <= stream_data_fifo[2];
                    end  
                end
          
                
      end        
    endgenerate

    // Add user logic here

    // User logic ends

    endmodule