Verilog分频电路用modelsim编译通过但仿真通不过求指导

module fenpin(clk,rst,s);
input clk,rst;
output s;
reg [13:0] count;
reg s;
always@(posedge clk or negedge rst)
if(!rst)
begin
s<=1'b0;
count<=14'b0;
end
else if(count==14'b11111111111111)
begin
s<=~s;
count<=14'b0;
end
endmodule
仿真代码如下：
module testbench;
reg clk , rst;
wire s;
initial
begin
clk=0;
rst=1;
#1 rst=0;
#1 rst=1;
end
always #50 clk=~clk;
fenpin u1(clk,rst,s);
endmodule
加上自加操作后，quartus编译有三个warning：
1、Critical Warning: No exact pin location assignment(s) for 3 pins of 3 total pins
2、Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
3、Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
仿真波形正确，但是在modelsim中无法仿真，没有warning