如何通过单个SPI传输从ADXL313读取多个字节？

我试图通过单个 SPI 传输从 ADXL313 读取多个字节。我可以读取设备 ID 寄存器。
如何使用多字节读取读取具有顺序地址（a1、a2、a3 ....）的设备的 6 个寄存器（每个 1 字节）？（如何传输虚拟字节，如果需要，如何在帧之间保持 PCS 位断言，以及何时以及如何读取数据（最后或与发送虚拟字节一起））
我是 SPI 的新手，正在以示例代码作为参考。
如果有人可以提供一些使用多字节读取的伪代码或实际代码，我将不胜感激。
谢谢。
示例代码：
void LPSPI0_init_master(void)
{
/*!
* LPSPI0 Clocking:
* ===================================================
*/
PCC->PCCn[PCC_LPSPI0_INDEX] = 0; /* Disable clocks to modify PCS ( default) */
PCC->PCCn[PCC_LPSPI0_INDEX] = PCC_PCCn_PR_MASK /* (default) Peripheral is present. */
|PCC_PCCn_CGC_MASK /* Enable PCS=SPLL_DIV2 (40 MHz func'l clock) */      |PCC_PCCn_PCS(6);
/*!
* LPSPI0 Initialization:
* ===================================================
*/
LPSPI0->CR = 0x00000000; /* Disable module for configuration */
LPSPI0->IER = 0x00000000; /* Interrupts not used */
LPSPI0->DER = 0x00000000; /* DMA not used */
LPSPI0->CFGR0 = 0x00000000; /* Defaults: */
/* RDM0=0: rec'd data to FIFO as normal */
/* CIRFIFO=0; Circular FIFO is disabled */
/* HRSEL, HRPOL, HREN=0: Host request disabled */

LPSPI0->CFGR1 = LPSPI_CFGR1_MASTER_MASK; /* Configurations: master mode */
/* PCSCFG=0: PCS[3:2] are enabled */
/* OUTCFG=0: Output data retains last value when CS negated */
/* PINCFG=0: SIN is input, SOUT is output */
/* MATCFG=0: Match disabled */
/* PCSPOL=0: PCS is active low */
/* NOSTALL=0: Stall if Tx FIFO empty or Rx FIFO full */
/* AUTOPCS=0: does not apply for master mode */
/* SAMPLE=0: input data sampled on SCK edge */
/* MASTER=1: Master mode */

LPSPI0->TCR = LPSPI_TCR_CPHA_MASK
|LPSPI_TCR_CPOL_MASK
|LPSPI_TCR_PRESCALE(2)
|LPSPI_TCR_PCS(0)
|LPSPI_TCR_FRAMESZ(15); /* Transmit cmd: PCS0, 16 bits, prescale func'l clk by 4, etc */
/* CPOL=1: SCK inactive state is high */
/* CPHA=1: Change data on SCK lead'g, capture on trail'g edge */
/* PRESCALE=2: Functional clock divided by 2**2 = 4 */
/* PCS=0: Transfer using PCS0 */
/* LSBF=0: Data is transfered MSB first */
/* BYSW=0: Byte swap disabled */
/* CONT, CONTC=0: Continuous transfer disabled */
/* RXMSK=0: Normal transfer: rx data stored in rx FIFO */
/* TXMSK=0: Normal transfer: data loaded from tx FIFO */
/* WIDTH=0: Single bit transfer */
/* FRAMESZ=15: # bits in frame = 15+1=16 */

LPSPI0->CCR = LPSPI_CCR_SCKPCS(4)
|LPSPI_CCR_PCSSCK(4)
|LPSPI_CCR_DBT(8)
|LPSPI_CCR_SCKDIV(8); /* Clock dividers based on prescaled func'l clk of 100 nsec */
/* SCKPCS=4: SCK to PCS delay = 4+1 = 5 (500 nsec) */
/* PCSSCK=4: PCS to SCK delay = 9+1 = 10 (1 usec) */
/* DBT=8: Delay between Transfers = 8+2 = 10 (1 usec) */
/* SCKDIV=8: SCK divider =8+2 = 10 (1 usec: 1 MHz baud rate) */

LPSPI0->FCR = LPSPI_FCR_TXWATER(3) /* RXWATER=0: Rx flags set when Rx FIFO >0 */
; /* TXWATER=3: Tx flags set when Tx FIFO <= 3 */

LPSPI0->CR = LPSPI_CR_MEN_MASK
|LPSPI_CR_DBGEN_MASK; /* Enable module for operation */
/* DBGEN=1: module enabled in debug mode */
/* DOZEN=0: module enabled in Doze mode */
/* RST=0: Master logic not reset */
/* MEN=1: Module is enabled */
}

void LPSPI0_transmit_16bits (uint16_t send)
{
while((LPSPI0->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT==0);
/* Wait for Tx FIFO available */
LPSPI0->TDR = send; /* Transmit data */
LPSPI0->SR |= LPSPI_SR_TDF_MASK; /* Clear TDF flag */
}

uint16_t LPSPI0_receive_16bits (void)
{
uint16_t recieve = 0;
while((LPSPI0->SR & LPSPI_SR_RDF_MASK)>>LPSPI_SR_RDF_SHIFT==0);
/* Wait at least one RxFIFO entry */
recieve= LPSPI0->RDR; /* Read received data */
LPSPI0->SR |= LPSPI_SR_RDF_MASK; /* Clear RDF flag */
return recieve; /* Return received data */
}
读取设备 ID：
LPSPI0_transmit_16bits(0xC000); //register at 0x00, first two bits are 1 for 'read' and 'multi-byte read' respectively, can't read multiple bytes though
LPSPI0_16bits_read = LPSPI0_receive_16bits();