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[问答]

如何管理200MHz的外部信号

你好，
我正在使用FPGA xc3s1400a-4ft256（Spartan 3A）来控制外部设备（FTDI USB外部控制器），如附图所示。
状态机被设计为在FTDI上生成WRITE信号并检查其他信号以验证传输是否完成。
该状态机运行在200MHz。
我不确定外部信号（状态机逻辑的输入）在使用前是否需要一些过程。
范围显示意外结果或解释问题？
这似乎是状态机没有理由改变状态。
随附的是带有望远镜信号的图像：
按预期结果停止
意外结果停止了
由于输入信号，运行过多的“抖动”？
在获取状态机逻辑之前，我可以定义任何约束来管理这些信号吗？
有什么想法或建议吗？ThanksJulio

以上来自于谷歌翻译


以下为原文

Hello,

I'm using a FPGA xc3s1400a-4ft256 (Spartan 3A) to control an external device (FTDI USB external controller) as show the attached picture.

A state machine is designed to generate the signals to WRITE on the FTDI and check others signals to verify if the transmission is completed. This state machine is running at 200MHz.


I'm not sure if the external signals (inputs to the state machine logic) need some process before use. The scope shows unexpected results or is a interpretation issue? That seems the state machine change state without reason.

Attached is a image with the scope signals:

  • Stopped with results as expected
  • Stopped with unexpected results
  • Running with too much "jitter" because the input signals?
Can I define any constraint to manage these signals before source the state machine logic?

Any idea or suggestions?
Thanks
Julio

回帖（3）

姚庭芳

2019-7-29 13:10:01
你好@ jcsistemas2001
我建议你对你的设计进行时序仿真。
还使用chipcope探测信号（状态机）并缩小问题范围。
谢谢，
维奈
--------------------------------------------------
------------------------------------------您是否尝试在Google中输入问题？
？
如果没有，你应该在发布之前。
此外，MARK这是一个答案，以防它有助于解决您的查询/问题。给予帮助您找到解决方案的帖子。

以上来自于谷歌翻译


以下为原文

Hello @jcsistemas2001 
 
I suggest you to run timing simulation of your design.
Also probe the signals (state machine) using chipscope and narrow down the issue.
 
Thanks,
Vinay
--------------------------------------------------------------------------------------------
Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution.
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云达贞

2019-7-29 13:15:02
你好@vuppala，
感谢您的回复。
我按照你的建议运行时序模拟。
结果还可以！
我需要提一下，状态机还使用一个外部触发器来通过第一个状态。
之后，取决于外部设备信号。
现在，根据第一个触发器的生成方式，我得到两个额外的结果：
-  Usingexternal函数发生器作为触发器（到状态机）结果不好。
- 使用微控制器作为触发器，结果没问题。
即使使用微控制器解决问题，我想知道是否存在针对此类问题的约束定义？
谢谢

以上来自于谷歌翻译


以下为原文

Hello @vuppala,
 
Thanks for your reply.
 
I follow your suggestion and run timing simulation. The results are OK!
 
I need to mention that the state machine also use one external trigger to pass the first state. After that, depend on the external device signals. 
 
Now, depending on how this first trigger is generated, I get two additional results:
 
- Using external function generator as trigger (to the state machine) the results are bad.
- Using a microcontroller as trigger, the results are OK.
 
Even when the issue is solved using a microcontroller, I would like to know if there are constraint definition for this kind of issues?
 
Thanks
 
 
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姚庭芳

2019-7-29 13:23:18
jcsistemas2001写道：
我不确定外部信号（状态机逻辑的输入）在使用前是否需要一些过程。
范围显示意外结果或解释问题？
这似乎是状态机没有理由改变状态。
在获取状态机逻辑之前，我可以定义任何约束来管理这些信号吗？
首先，所有状态机输入信号必须与状态机的时钟同步。
从外部设备进入的信号必须先与FPGA时钟同步，然后才能将它们提供给状态机。
----------------------------是的，我这样做是为了谋生。

以上来自于谷歌翻译


以下为原文

jcsistemas2001 wrote:
 
I'm not sure if the external signals (inputs to the state machine logic) need some process before use. The scope shows unexpected results or is a interpretation issue? That seems the state machine change state without reason.
 
Can I define any constraint to manage these signals before source the state machine logic? 
First, all state machine input signals must be synchronous to the state machine's clock. Signals coming in from the external device must be synchronized to the FPGA clock before you can present them to the state machine.
 
 
----------------------------Yes, I do this for a living.
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