尝试编程spartan3s50an fpga错误

您应该上拉变量选择引脚VS [2：0]。
来自Spartan 3 Generatuion用户指南
UG332：
-  Gabor



以下为原文

You should pull up the Variant select pins VS[2:0].  From the Spartan 3 Generatuion User's guide
ug332:
 

-- Gabor

来自UG332 v1.6
当iMPACT 9.1i配置Spartan-3AN FPGA时，它首先对内部SPI Flash PROM进行编程。
完成此配置后，将触发重新启动，并且FPGA将从内部SPI PROM进行自我配置。
当重启被触发时，模式引脚M [2：0]被采样。
要使配置成功完成，FPGA模式选择引脚必须设置为M [2：0] =，这是内部主SPI模式。
如果从iMPACT进行配置，并且模式引脚设置为JTAG模式M [2：0] =，则FPGA的配置将无法完成。
要完成FPGA的配置，您只需将模式引脚更改为内部主SPI模式，并将PROG引脚脉冲触发配置，或通过iMPACT重新配置。
在iMPACT 9.2i及更高版本中，您可以选择直接通过JTAG模式配置FPGA，也可以编程内部SPI PROM，然后通过内部主SPI模式进行配置。
如果您使用IMPACT 9.2i或更高版本，则下载到FPGA或内部SPI闪存应该已经成功。
如果您使用的是早期版本的IMPACT，则MODE和VSEL引脚对于成功至关重要，并且（正如Gabor指出的那样）VSEL引脚设置不正确。
Spartan-3AN系列在VSEL引脚上有内部上拉电阻，您无需将任何其他内容连接到VSEL引脚（除非配置后VSEL引脚是用户IO引脚）。
当然，即使使用JTAG，也必须取消激活PROG_B（必须为高电平）才能使FPGA配置或下载成功。
您使用的是什么版本的IMPACT？
IMPACT是否为FPGA返回正确的ID代码？
IMPACT会发现内部SPI闪存吗？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
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以下为原文

From UG332 v1.6

When iMPACT 9.1i configures the Spartan-3AN FPGAs, it first programs the internal SPI Flash PROM. After this configuration is complete, a reboot is triggered and the FPGA configures itself from the internal SPI PROM. When the reboot is triggered, the mode pins M[2:0] are sampled. For the configuration to complete successfully, the FPGA mode select pins must be set to M[2:0] = <0:1:1>, which is the Internal Master SPI mode.


If you are configuring from iMPACT and your mode pins are set to JTAG mode M[2:0] = <1:0:1>, configuration of the FPGA will not complete. To finish configuration of the FPGA, you can simply change the mode pins to Internal Master SPI mode and pulse the PROG pin to trigger configuration, or reconfigure through iMPACT.


In iMPACT 9.2i and later, you have the option to either configure the FPGA directly through JTAG mode or to program the Internal SPI PROM and then configure through Internal Master SPI mode.

If you are using IMPACT 9.2i or later, your download to the FPGA or internal SPI flash memory should have been successful.
 
If you are using an earlier version of IMPACT, your MODE and VSEL pins are critical for success, and (as Gabor points out) the VSEL pins are set incorrectly.  Spartan-3AN family has internal pulllups on the VSEL pins, you need not connect anything else to the VSEL pins (unless the VSEL pins are user IO pins after configuration).
 
And of course, PROG_B must be de-asserted (must be HIGH) for FPGA configuration or download to be successful, even when using JTAG.
 
What version of IMPACT are you using?  Does IMPACT return the correct ID code for the FPGA?  Does IMPACT discover the internal SPI flash memory?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
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4. Do not post a new topic or question on someone else's thread, start a new thread!
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我一直在追逐这个问题超过一年。
似乎在文档UG332，DS557和其他几个文档中有一些不成文或难以找到的内容。
我已经读了这么多。
我有两个硬件设计都使用XC3S50AN-TQG144
设计1）一旦FPGA启动并运行，M0，M1M2都被指定为输入。
如果通过三态缓冲器将它们提供给程序并运行功能，则使它们能够上拉和下拉，并在电路板PU脉冲（100mS）期间强制进入三态。
这允许1k上拉和下拉电阻器在该初始时段期间定义它们的状态。
两个跳线将电阻连接到+ 3.3v或gnd，具体取决于我是要编程还是运行。
正常运行时M2 = 0，M1 = 1，M0 = 1
对于JTAG编程，M2 = 1，M1 = 0，M0 = 1。
VS2，VS1，VS0使用相同的硬件系统，但正常读取的1k电阻总是连接1,0,1。
PUC_B通过1K电阻永久连接到3.3V。
INIT_B和PROG_B通过1k电阻拉至3.3v。
DONE通过1k和LED串联连接到3.3v，以便我可以看到它是否保持低电平。
结果：我总是可以对闪存和FPGA进行编程（第一个影响选项），但总是失败并且DONE为低（完成LED低）但是它已经成功编程，我每次都可以100％校正校验和来验证它。
它运作良好。
唯一的烦恼是在影响报告失败之前的长时间超时。
设计2）
与设计1相同，但是一旦FPGA启动并运行，M2，M1，M0，VS2，VS1，VS0引脚都将用作输出。
它们具有相同的上拉/下降布置，并具有相同的跳线布置。
为了防止这些引脚驱动的电路以错误的方向拉动它，我使用非反相cmos门来缓冲实际负载。
这是一个更简单的解决方案。
结果：在程序模式下：与设计1相同 - “完成失败”但编程实际上成功了。
在运行模式下：我可以100％成功编程，并且完成了很高的!!
如果我不需要跳线 - 我可以在运行状态下硬线M2，M1，M0。
上述两种情况都是使用Impact 10.1和12.4发生的，除了12.4在失败之前似乎有一个令人讨厌的超时！
我实际上可以在超时期间再次打开电源并获得“成功”，因为这样可以让DONE变高。
Xilinx用于测试此功能的确切电路是什么？
有模仿的电路吗？
你可以说我的设计2是解决方案，但为什么呢？
为什么它在运行模式下编程？
听起来我实际上并没有“触及现场”



以下为原文

I have been chasing this problem for over a year. It seems that there is something unwritten or difficult to find in the documentation UG332, DS557 and several others. I have read so much on this.
 
I have two hardware designs both using XC3S50AN-TQG144
 
Design 1) M0,M1M2 are all designated as inputs once the FPGA is up and running. To enable them to be pulled up and down for the program and run functions if feed them through a tri-state buffer which is forced in to tri-state during the board PU pulse (100mS). That allows the 1 k pull up and down resistors to define their states during that initial period. Two jumpers connect the resistors to +3.3v or gnd depending on whether I want to program or run.
M2=0, M1=1,M0=1 for normal running
M2=1 ,M1=0 , M0=1 for JTAG programming.
The same hardware system is used for VS2,VS1,VS0 but the 1 k resistors connect always 1,0,1 for the normal read.
PUC_B is connected permanently to 3.3V via 1K resistor..
INIT_B and PROG_B are pulled to 3.3v via 1k resistors.
DONE is connected to 3.3v via a 1k and LED in series so that I can see if it stays low.
Result: I can always program the flash and FPGA (first Impact option) but is always fails with DONE low (done led low) however it has successfully programmed and I can read the checksum 100% correct every time to verify it. It functions fine. The only irritation is the long timeout before impact reports that it has failed.
 
Design 2)
That same as design 1 but M2,M1,M0,VS2,VS1,VS0 pins are all used as outputs once the FPGA is up and running.
They have the same arrangement of pull-up/downs with the same arrangement of jumpers. To prevent the circuit that those pins drive from pulling them in the wrong direction I use non-inverting cmos gates to buffer the actual loads.
It is a simpler solution.
Result:  In program mode: the same as design 1 - "done failed to go high" but programming actually succeeded.
In run mode: I can program 100% successfully and done does go high!! If fact I don't need the jumpers - I can hard wire M2,M1,M0 in the run state.
 
Both of the above situations occur using Impact 10.1 and 12.4 except that 12.4 seems to have an annoyingly longer timeout before fail!  I can actually power off then on again during that timeout and get a "succeed" because that lets DONE go high).
 
 
What exact circuit to Xilinx use for testing this functionality?
Is there a circuit to emulate?
You could say that my design 2 is the solution but why? and why does it program in the run mode? It sounds like I have not actually  "touched the spot"
 
 

正如在本主题中已经提到的那样，你应该将VS和M引脚设置为“运行模式”
在冲击完成加载后，FPGA要求从闪存加载自身
闪光。
注意，M引脚不需要设置为JTAG进行编程。
JTAG
无论模式如何都会有效。
“JTAG模式”的目的是防止
当您没有其他配置源时，FPGA会尝试自我配置。
您
可能会注意到较新的设备不再具有此模式，因为任何“奴隶”
模式实现了同样的目的。
对于DONE引脚问题，与上拉串联的LED可能就足够了
保持DONE低于逻辑阈值。
我建议并联一个电阻
您现在使用LED +电阻（从DONE引脚直接连接到Vcc）。
交替
如果您在此DONE行上只有一个设备，则可以更改您的bigten设置
“Drive DONE high”或“Use internal DONE pipe”强制将DONE引脚拉高
没有上拉或使用内部DONE信号而不是等待
把自己钉在高处。
重要的是要注意除非内部信号，否则DONE是双向引脚
用来。
它在多FPGA系统中的目的是允许所有芯片退出
同时配置。
-  Gabor
-  Gabor



以下为原文

As already noted in this thread, you should have VS and M pins set for "run mode" in
order for the FPGA to load itself from the flash after impact has completed loading
the flash.  Note that the M pins do not need to be set to JTAG for programming.  JTAG
will work regardless of the mode.  The purpose of the "JTAG mode" is to prevent the
FPGA from trying to self-configure when you have no other configuration source.  You
may note that newer devices no longer have this mode, since any of the "slave"
modes accomplish the same purpose.
 
As to the DONE pin problem, an LED in series with the pullup may be enough to
keep DONE below the logic threshold.  I would suggest adding a resistor in parallel
with the LED + resistor you have now (from DONE pin directly to Vcc).  Alternately
if you only have one device on this DONE line, you can change your bigten settings
to "Drive DONE high" or "Use internal DONE pipe" to either force the DONE pin high
without a pullup or to use the internal DONE signal rather than waiting for the
pin itself to go high.
 
It's important to note that DONE is a bidirectional pin unless the internal signal
is used.  Its purpose in a multi-FPGA system is to allow all chips to exit
configuration at the same time.
 
-- Gabor
-- Gabor