请问Spartan 6 DCM用户指南UG382.PDF版本1.7图3-15 DCM的驱动PLL有错误吗？

我注意到图3-15已经过各种编辑。
我认为DCM CLKIN（波形2）和CLKFBIN（波形3）的两个输入应该始终同意，前提是反馈环路闭合，DCM相位控制被锁定。
因此，我认为该图中的波形3必须是DCM的CLK0处的信号，而不是DCM的CLKFB处的信号，如图3-15中所示。
我认为CLKFBIN的信号与waveform2相同。
当然假设通过BUFG的延迟与通过IBUFG的延迟相同。
如果我不了解DCM的工作原理，有人可以纠正我吗？
否则，XILINX可以将此添加到此文档的勘误表中吗？
谢谢

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以下为原文

I notice Figure 3-15 has undergone various edits.

I think that the two inputs to the DCM CLKIN (waveform 2) and CLKFBIN (waveform 3) should ALWAYS agree in phase provided the feedback loop is closed that the DCM phase control is locked.
Therefore, I think that waveform 3 in this drawing must be the signal at CLK0 of the DCM and NOT the signal at CLKFB of the DCM as annotated in Figure 3-15. I think that the signal at CLKFBIN is the same as waveform 2. This is assuming of course that the delay through BUFG is the same as the delay through IBUFG.

Can someone please correct me if I am not understanding how the DCM works? Otherwise, can XILINX please add this to the errata for this document?

Thanks

杨玲

2019-6-26 06:27:33

实际上DCM旨在消除IBUFG延迟，以便CLKFB引脚匹配
焊盘输入（1）的定时而不是CLK0输入（2）。
BUFG延迟实际上是相当的
比IBUFG延迟大一点，但它在反馈回路中被删除。
在
Spartan 6我认为有些选项会影响基于DCM的绝对延迟
是否要删除输入延迟（我相信时钟向导指的是
这是“系统同步”，意味着来自DCM的时钟与“系统”相匹配
输入板上的时钟）。
所以我很确定绘图是准确的。
- Gabor
- Gabor
在原帖中查看解决方案

以上来自于谷歌翻译

以下为原文

Actually the DCM is designed to remove the IBUFG delay so that the CLKFB pin matches the
timing of the pad input (1) rather than the CLK0 input (2). The BUFG delay is actually quite a
bit larger than the IBUFG delay, but it is removed by virue of being in the feedback loop. In
Spartan 6 I believe there are options that affect the absolute delay through the DCM based
on whether or not you want to remove the input delay (I believe the clocking wizard refers to
this as "system synchronous" meaning that the clock from the DCM matches the "system"
clock at the input pad).

So I'm pretty sure that the drawing is accurate.

-- Gabor
-- GaborView solution in original post

杨玲

2019-6-26 06:45:19

实际上DCM旨在消除IBUFG延迟，以便CLKFB引脚匹配
焊盘输入（1）的定时而不是CLK0输入（2）。
BUFG延迟实际上是相当的
比IBUFG延迟大一点，但它在反馈回路中被删除。
在
Spartan 6我认为有些选项会影响基于DCM的绝对延迟
是否要删除输入延迟（我相信时钟向导指的是
这是“系统同步”，意味着来自DCM的时钟与“系统”相匹配
输入板上的时钟）。
所以我很确定绘图是准确的。
- Gabor
- Gabor

以上来自于谷歌翻译

以下为原文

Actually the DCM is designed to remove the IBUFG delay so that the CLKFB pin matches the
timing of the pad input (1) rather than the CLK0 input (2). The BUFG delay is actually quite a
bit larger than the IBUFG delay, but it is removed by virue of being in the feedback loop. In
Spartan 6 I believe there are options that affect the absolute delay through the DCM based
on whether or not you want to remove the input delay (I believe the clocking wizard refers to
this as "system synchronous" meaning that the clock from the DCM matches the "system"
clock at the input pad).

So I'm pretty sure that the drawing is accurate.

-- Gabor
-- Gabor

陈玉筠

2019-6-26 07:03:32

使用DCM驱动PLL的一个要点是PLL不能对相移进行精细控制 - DCM就是如此。
相反，DCM会增加抖动，PLL会将其删除。
因此，如果您想要一个相移低抖动时钟，那么您可以使用此级联。
使用DCM进行相移的整个想法是它可以改变CLKIN和CLKFB之间的相位关系 - 如果你要求DCM的2ns相移，那么CLKFBIN将比CLKIN晚2ns（除了可选的补偿）
对于Gabor提到的IBUFG）。
Avrum

以上来自于谷歌翻译

以下为原文

One of the main points for using DCM driving PLL is that the PLL doesn't have fine control over phase shifting - the DCM does. Conversely, the DCM adds jitter, the PLL removes it. So, if you want a phase shifted low jitter clock, then you use this cascade.

The whole idea of using the DCM for phase shifting is that it can change the phase relationship between CLKIN and CLKFB - if you ask for a 2ns phase shift from the DCM, then CLKFBIN will be 2ns later than CLKIN (in addition to the optional compensation for the IBUFG that Gabor mentioned).

Avrum

李耘蝶

2019-6-26 07:08:55

非常感谢Arum和Gabor。
我很感激你的见解。

以上来自于谷歌翻译

以下为原文

Thanks very much Arum and Gabor. I appreciate your insight.

邢东

回帖（4）

杨玲

杨玲

陈玉筠

李耘蝶

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