如何替换Spartan-6代码中的BUFGDLL？

BUFGDLL从未存在过 - 它始终是特定配置中DLL和BUFG的简写。
真正的联系是： 
- 时钟在时钟引脚上进入FPGA 
- 时钟通过输入缓冲区（IBUFG） 
-  IBUFG的输出转到DCM的CLKIN 
-  DCM的CLK0输出进入BUFG 
-  BUFG输出是用于设计的缓冲时钟（BUFGDLL的输出） 
-  BUFG输出也进入DCM的CLKFB输入
构建它的最简单方法是使用CoreGen的Clocking Wizard。
它将实例化所有单元并为您连接所有信号。
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以下为原文

A BUFGDLL never existed - it was always a shorthand for a DLL and a BUFG in a particular configuration.
 
The real connection is:
  - clock comes into the FPGA on a clock capable pin
  - clock goes through an input buffer (IBUFG)
  - output of IBUFG goes to CLKIN of DCM
  - CLK0 output of DCM goes to BUFG
  - BUFG output is the buffered clock used for your design (the output of the BUFGDLL)
  - BUFG output also goes to the CLKFB input of the DCM
 
The easiest way to build this is to use the Clocking Wizard from CoreGen. It will instantiate all the cells and connect all the signals for you.
 
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