H，
线路（模拟侧）环回很难做到，并保持信号完整性。
因此，近端环回通常需要删除连接到传输的任何内容，因为这可能会导致问题。
这就是为什么逻辑环回通常用于验证GT的逻辑是否正常，然后在线路上使用环回插头来验证物理模拟线路层。
可能还有其他打嗝：
https://www.xilinx.com/support/answers/53107.html
Austin Lesea主要工程师Xilinx San Jose
以上来自于谷歌翻译
以下为原文
h,
Line (analog side) loopbacks are tough to do and keep the signal integrity perfect.
So, a near end loopback often requires you remove anything attached to the transmit as that can cause problems.
That is why the logic loopback is often used to verify the logic to/from the GT is OK, followed by using a loopback plug on the line to verify the physical analog line layer.
There may be other hiccups as well:
https://www.xilinx.com/support/answers/53107.html
Austin Lesea
Principal Engineer
Xilinx San Jose
H，
线路（模拟侧）环回很难做到，并保持信号完整性。
因此，近端环回通常需要删除连接到传输的任何内容，因为这可能会导致问题。
这就是为什么逻辑环回通常用于验证GT的逻辑是否正常，然后在线路上使用环回插头来验证物理模拟线路层。
可能还有其他打嗝：
https://www.xilinx.com/support/answers/53107.html
Austin Lesea主要工程师Xilinx San Jose
以上来自于谷歌翻译
以下为原文
h,
Line (analog side) loopbacks are tough to do and keep the signal integrity perfect.
So, a near end loopback often requires you remove anything attached to the transmit as that can cause problems.
That is why the logic loopback is often used to verify the logic to/from the GT is OK, followed by using a loopback plug on the line to verify the physical analog line layer.
There may be other hiccups as well:
https://www.xilinx.com/support/answers/53107.html
Austin Lesea
Principal Engineer
Xilinx San Jose
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